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about low power design for pipeline adc

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lhlbluesky

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low power design and pipelining

i want to design a pipelined adc which is low power,
the resolution is 10bits,then
can anyone tell me how to decide the resolution of every stage,
someone tell me the 2.5 bit per stage is the best power-optimized,is that right?
can anyone give me some advice?
besides,for low power design ,what considerations should i take?
please help me.
any advice or related papers are expected,thanks first!
 

mickey_melomane

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low power pipeline adc

Refer to theses of people working in that area... One such I know is

Low-Voltage Pipeline A/D Converter - Lei Wu (thesis at Oregon State University
 

naalald

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Hi,
For 10 and less resolutions generally 1.5 bits per stage is used.
For power optimization you can use capacitor scaling.
Also you can decide on the S/H for the input to eliminate it or not (Eliminating the input S/H saves power and relaxes the noise requirements and thus improving the performance if it's possible). It depends on the speed of the ADC and the implementation tools.
You can obtain more information from thesis like this one (Abo, Berkeley, 1999).
Here it is;
Hope it helps you.
 
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naalald

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Hi,
As you know a pipeline ADC consists of several sub-ADC stages. These sub-ADCs can be a 1-bit, 2-bit or higher resolution sub-ADCs. But if you use a 1.5-bit, 2.5-bit or mor e stage for these sub-ADCs (the 0.5-bit referes to an extra redundant LSB bit which is added to the MSB of the next stage), the resulting structure will have the capability of error correction. For more informatiom you can refer to the literiture in pipeline ADC such as the book "V. D. Plassche, Kluwer 2003".
 

stormknight

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Power depends on the speed very much!
For low power, 1.5bit/stage is better, and capacitor scaling is a good choice.
 

sayed_askari

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Thx

Added after 2 minutes:

Hi can I download Abo Thesis??
 

naalald

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Hi,
You can download articles when:
- It's 7 days after your membership
- You have enough points for download
 

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