About generated_clock

[TomCIC]

Hi everyone,

I have some questions about generated clocks.

When a divider/multiplier is used to generate a clk_out accoring to the input clk_in, then we define clk_out as a generated clock from clk_in. In the synthesis:
1) Do we need to set the generated clk_out as ideal or dont_touch?
2) Would the synthesis tool consider the delay introduced by the divider/multiplier? (I mean the gate delays in the divider/multiplier)

If clk_in is used to generate clk_out and then clk_out is further used to generate clk_out2, and clk_out is not used anywhere else, do we need to define the relationship between clk_in and clk_out? Or just define the relationship between clk_in and clk_out2?

If a MUX is inserted to select the output clock from several input clocks, do we need to define the output clock as a generated clock? If we need to, then which input clock should be applied as the source?

Sometimes a clock divider would be described in RTL and the Q or QN of a FF can be used to trigger following FFs. In this case, the Q or QN pin of that FF is used as a clock. Do we need to define the Q or QN pin of that FF as a generated clock?

Thanks in advance.

Best
Tom

 

[TomCIC]

About geenrated clocks

Hi everyone,

I have some questions about the geenrated clocks.

When a divider/multiplier is used to generate an output clock clk_out according to the input clock clk_in, we need to define the clk_out as a generated clock sourced from clk_in. In the synthesis:
1) Do we need need to define the clk_out as ideal or dont_touch?
2) Would the synthesis tool consider the gate delay of the divider/multiplier?

If we insert a MUX into the clock line and choose the output clock from several input clocks, then:
1) Do we need to define the output of the MUX as a generated clock?
2) In synthesis, which input clock's frequency should be used for the output clock?
3) Would the synthesis tool consider the delay of the MUX?

Thanks a lot!

Best
Tom

 

[ThisIsNotSam]

I think you are mixing up two concepts.

A "divided clock" means that the frequency was divided. It doesn't mean a divider was instantiated for you. You still have to code it yourself. Most likely you will use flops for that, so there is no "divider" gate delay to be accounted for.

Synthesis needs all clocks to be defined unambiguously. That means all generated clocks too. Otherwise you start seeing results that are really confusing, clock relationships that don't really exist, etc.

 

[TomCIC]

I think you are mixing up two concepts.

A "divided clock" means that the frequency was divided. It doesn't mean a divider was instantiated for you. You still have to code it yourself. Most likely you will use flops for that, so there is no "divider" gate delay to be accounted for.

Synthesis needs all clocks to be defined unambiguously. That means all generated clocks too. Otherwise you start seeing results that are really confusing, clock relationships that don't really exist, etc.

Thank you for the reply.

So I think when I instantiate a divider, I still need to use the generated_clock to define the relationship bwtween the input and output clocks of that divider. The "gate delay" is the the component delay inside the divider, e.g., the delays of combinational gates and flip-flops. The edges of generated clock and the source clock can be perfectly alligned. However, due to the internal delays of a divider, these edges cannot be alligned perfectly. So I guess synthesis may not take these dealys into account? Correct me if you think anything is wrong...

 

[ThisIsNotSam]

You are making it more complicated than what it really is. There is no divider gate delay to be taken into account at all. You are generating a clock, not a signal.

Just use the generated clock commands accordingly.

 

[slutarius]

1) Do we need need to define the clk_out as ideal or dont_touch?
At synthesis stage, all clock latencies will be 0.
You don't need to worry about "clock delay" because we can set them ideal.

2) Would the synthesis tool consider the gate delay of the divider/multiplier?
In synthesis, no.

About clock devider, whether you have a divider instance or a divider code, you need to define generated clock as well.
The point is that, you need to assure the generated clock pin/port MUST have the logic path back to its master source, with respect to the sense relationship from what you defined.

1) Do we need to define the output of the MUX as a generated clock?
You can define a generated clock with divide_by 1 for the fastest one. Or, simply apply set_case_analysis to the selector to let the fastest clock propagate to FF in MUX fan-outs

2) In synthesis, which input clock's frequency should be used for the output clock?
The fastest one.

3) Would the synthesis tool consider the delay of the MUX?
In term of timing path, No. Cell on clockline has nothing todo in synthesis timing report.
But Tool will check the validity of clock definition in varius points of view.