1) Do we need need to define the clk_out as ideal or dont_touch?
At synthesis stage, all clock latencies will be 0.
You don't need to worry about "clock delay" because we can set them ideal.
2) Would the synthesis tool consider the gate delay of the divider/multiplier?
In synthesis, no.
About clock devider, whether you have a divider instance or a divider code, you need to define generated clock as well.
The point is that, you need to assure the generated clock pin/port MUST have the logic path back to its master source, with respect to the sense relationship from what you defined.
1) Do we need to define the output of the MUX as a generated clock?
You can define a generated clock with divide_by 1 for the fastest one. Or, simply apply set_case_analysis to the selector to let the fastest clock propagate to FF in MUX fan-outs
2) In synthesis, which input clock's frequency should be used for the output clock?
The fastest one.
3) Would the synthesis tool consider the delay of the MUX?
In term of timing path, No. Cell on clockline has nothing todo in synthesis timing report.
But Tool will check the validity of clock definition in varius points of view.