Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

about generate construct. can anybody help?

Status
Not open for further replies.

greendraw

Newbie level 4
Newbie level 4
Joined
Jul 1, 2009
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Russia
Activity points
1,315
generate for (i=0;

i want to use "generate"-"endgenerate" construction to instantiate multiply module without typing them all. and i ask you decribe me how i can write description.
so i want to unite same outputs from single-type modules and and if one of this outputs not is '1' then i want choose this module.
i think it must be liike this


Code:
...
generate for (i=0; i<Count; i= i +1)
   begin: mult
        unit [i] ( ..., myout[i]);
        ...
         if myout[] == b"1...11" then
            allout = VCC;
        else
            allout = GND;
        end if;
    end
endgenerate
...

i'm a newbie in verilog and don't know how do code correctly. can anybody help me?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top