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about gatecout at .13 & .18 TSMC process

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tavidu

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0.13um area gate count

Hi
First I compile my design with .18 TSMC library.
The library area : 17,000,000
The gate count: 17,000,000/10 = 1,700,000 (NAND2X1 library area : 10)

Then I compile the same design with .13 TSMC library.
The library area : 15,460,000
The gate count: 15,460,000/5.1 = 3,000,000 (NAND2X1 library area : 5.1)

In my opion, the same design should have same gate count , although I use different process library. I am confused with that result. The result differs too much:(

Anyone can tell the result?

Thanks
 

leeenghan

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gate count tsmc

Hi,

The area reduction seem to be too little when move from 0.18um to 0.13um. If the timing constraint is the same, then it should be very easy to meet timing in 0.13um, result in further area reduction.

Is there macro in the design? Can it be you are using the same macro in both implementation? If this is the case, you should take away the macro area from the total area.

To find out the cause, you can also break down the area into combinatiorial area, flip-flop area, clock tree area etc etc. Since the NAND gate area is about halve in 0.13um, the area in different cateorgies should also be in that order.

Regards,
Eng Han
www.eda-utilities.com
 

tavidu

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Hi,
Thanks for your reply.
Now I know the reason.
when I compile using .13 library, i add commands as following:
set_ideal_net [all_high_fanout -th 100];
set_dont_touch [all_high_fanout -th 100];

But when using .18 library, the script doesn't including the commands above.

When i delete the commands, the compile area is OK for .13&.18 as i expected.
But i don't why the two commands will effect the compile area too much.

Thanks
 

moneychaser

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For high fan out nets, a lot of buffering may have been inserted for .18. But as you set_dont_touch for .13, that buffering may not have been inserted, resulting in a smaller design.
 

papertiger

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Those setting are reserved for reset/clocks.

You should identify those clock/reset net instead of using 100 fanout.
 

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