Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

About Gate Level Simulation

Status
Not open for further replies.

fireman

Junior Member level 2
Joined
Sep 16, 2002
Messages
24
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
126
Could someone tell me how to do Gate Level Simulation? Thanks
 

darkness

Newbie level 4
Joined
Jan 15, 2003
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
52
Gate Level Simulation

Gate level simulation simulates an ASIC/FPGA project after logic synthesis. It can simulate a system considering gate delay without considering wiring delay.
 

alledauser

Member level 1
Joined
May 16, 2001
Messages
40
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
287
Perform synthesis and placement/routing steps (Foundation/Alliance or Quartus), replace your top level design file in your rtl workbench with the one generated by your implementation tool (Foundation/Alliance or quartus). You may need to do some changes especially for initialization.
regards
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top