About dft FAULT COVERAGE

[HolySaint]

dft fault coverage

here is the some part of the coverage log

Begin deterministic ATPG: #uncollapsed_faults=1555224, abort_limit=10...
Warning: Chain test pattern failed contention checking (ID=481). (M430)
0 64892 1485633 1232/2286/1052450 10.92% 531.27
Warning: 1036714 faults aborted during contention prevention. (M139)

how can i fix the contention?
how can i find the ID=481 gate?

 

[HolySaint]

dft fault

waiting 4 hlp

 

[amnesia13]

chain test pattern failed contention checking

Hi,

Personnally, I would setup a basic "scan-like" simulation to check clocks, reset and scan chains integrity. I am quite sure that you will see an X value on some scan path.

 

[santhosh007]

fault coverage dft

here is the some part of the coverage log

Begin deterministic ATPG: #uncollapsed_faults=1555224, abort_limit=10...
Warning: Chain test pattern failed contention checking (ID=481). (M430)
0 64892 1485633 1232/2286/1052450 10.92% 531.27
Warning: 1036714 faults aborted during contention prevention. (M139)

how can i fix the contention?
how can i find the ID=481 gate?

There is contention in the design thats wat it says. Check that particular instrance if it has bidi force to Z. so that you will have contention.

 

[sunilbudumuru]

Hi...,

you have two questions.

1. how can i fix the contention?

During test logic insertion itself you should take care of contentions. Verify the three-state buses, bidi buses, bus holders in the design. if memories are present, check the memory outpt state.
Or u can ignore generating the patterns if it doesn't effect the coverage. But it is always beter to fix it.

2. how can i find the ID=481 gate?
It is purely tool dependent. Follow the tool related commands to back trace from the failed the gate. By the way, which tool r u using?

Added after 9 minutes:

Hi...,

you have two questions.

1. how can i fix the contention?

During test logic insertion itself you should take care of contentions. Verify the three-state buses, bidi buses, bus holders in the design. if memories are present, check the memory outpt state.
Or u can ignore generating the patterns if it doesn't effect the coverage. But it is always beter to fix it.

2. how can i find the ID=481 gate?
It is purely tool dependent. Follow the tool related commands to back trace from the failed the gate. By the way, which tool r u using?

 

[HolySaint]

i use the DFTC to generate inserted netlist,but the estimate_test_coverage is the commond in TMAX
when i put the inserted scan netlist into TMAX, it has error like this:

Error: Memory (deinter_ram/mem) has no write ports and no init file. (B24-1)

but in the tmax script, i add this:

read netlist -format verilog sim_lib/rom.v
set black_box rom

and in the rom, it initialed like this:

initial
$readmemb("rom_verilog.rcf", mem );

so i dont know how to clear the error........

Added after 1 minutes:

and the .v and .rcf files are generated by memory compiler

 

[sunilbudumuru]

Okay,

1. Make sure u r using a black box'ed memory model with tri-stated output. (verilog sim_lib/rom.v) as mentioned below.

2. Provide a memory initialization file together with the memory model.

3. If you want u can comment the following

initial
$readmemb("rom_verilog.rcf", mem );

and proceed further. Anyway u r not generating the memory test paterns right.

///////////////////////////////////////////////////////
module MY_ROM ( oe, addr, data_out );
input oe; // output control
input [3:0] addr; // 16 words
output [7:0] data_out; // 8 bits per word
reg [7:0] data_out; // output holding register
reg [7:0] memory [0:15] ; // memory storage
always @(oe or addr)
if (!oe) data_out = memory[addr];
else data_out = 8'bZZZZZZZZ;
initial $readmemh("rom_image.dat", memory);
endmodule
//////////////////////////////////////////////
/////////////////////////////////////////////
and your initialization file looks as below.

0000000000000001
0000000000000010
0000000000000100
..
..
..
/////////////////////////////////////////////

I guess (not sure), you can generate the SCAN test patterns without rom initialization file. We've generated the SCAN test patterns without memory initialization file with memories being Black-Boxed as coded above.

Please make sure. And I guess it works for u.



in your case TMAX is expecting the memory initialization file

 

[madhavisai]

hey u doing work on which tool
actually i require help for Cadence Encounter Test architect tool
can u give the required material plzzzzzzzzzzzzz

 

[HolySaint]

i use dftc