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about design ware asyn memory model

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Hi all

Does anybody have use latch based memory model "Dw_ram_r_w_a_lat" of

designware library?

My problem is that the glitch from the address decode circuit

makes the input data be writen to the unexpected memory location.

How can I deal with this the glitch problem?

Is there any suggestion? or any reference ?

Thank you~~
Best Regards,
 

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