about delay line design for DLL

[slchen]

Dear all:

I am designing a VCDL (inverter chain)for regulated-type DLL.
The target spec. (delay) of the VCDL is 1ns for 1GHz input clock.
Now, the delay of the VCDL is less than 1ns.
So, I want to increase the delay to meet the target spec.
There are two ways to increase delay.
1. increase the number of stages
2. increase the delay of each inverter

Could you explain that which one is better for DLL design.
What is the advantages and drawbacks of these two solutions?

Thanks for your kindly help.
slchen