ABOUT CONFIG ALTERA ACEX By MicroProcessor & Flash

[TERRYWU3]

Dear All:
Do you ever use low price method to config Altera FPGA ?
Like CPU or CPLD+FLASH
Although I read Altera documents but I am not sure my design is right

I want use 8051 + flash to config ACEX 1k100
Can you give me a reference Design , Very thanks ^^

my Email : terrywu3@pchome.com.tw

 

[sucan]

I've successfully config xilinx FPGA spartan-II X2S150 through JTAG mode using ARM core MCU AT91FR4081(atmel corporation).
I don't know if altera has the referense design, but xilinx is. Its referense design is application note 058 including the C code. I think it will be very helpful to your design. Good luck.

 

[cd505]

u can find the soruce code in @ltera's web.the key is 16/8bit ---> 1 bit.

 

[Ohh2]

Re: ABOUT CONFIG ALTERA ACEX By MicroProcessor & Flas

See this page for Altera devices:

http://www.@ltera.com/support/devices/programming/configuration/sup-configuration.html[/quote]

 

[yev15]

Re: ABOUT CONFIG ALTERA ACEX By MicroProcessor & Flas

You can look at the 3rd party development boards for Acex. Usually, the schematic is attached to the datasheet.

 

[YUV]

Re: ABOUT CONFIG @ltera ACEX By MicroProcessor & Flas

Dear All:
Do you ever use low price method to config @ltera FPGA ?
Like CPU or CPLD+FLASH
Although I read @ltera documents but I am not sure my design is right

I want use 8051 + flash to config ACEX 1k100
Can you give me a reference Design , Very thanks ^^

my Email : terrywu3@pchome.com.tw

Search application note 116 "Configuring SRAM-Based LUT Devices" on Altera's site.

 

[eternal_nan]

Re: ABOUT CONFIG ALTERA ACEX By MicroProcessor & Flas

Hi,

Any @ltera and Xilinx device can be configured through JTAG, meaning you only need to be able to drive TCK, TRST, TDI, TDO and TMS. This can be done using GPIO pins on the 8051. Basically, you would store the
binary image of the FPGA program somewhere in the 8051's EDATA (external data, if I remember correctly) memory segment, then you
would use the micro to read out the mentioned memory locations and
toggle the jtag interface lines correspondingly. It should be fairly easy,
since TCK (the test clock) can be as slow as you need it to be.

 

[TurboPC]

Re: ABOUT CONFIG ALTERA ACEX By MicroProcessor & Flas

Hi,

In Quartus, set the compiler option to create a TTF file. For MaxplusII, I think it is always generated. The TTF file contains all the byte/bits that need to be transferred to the ACEX devices.

Include the TTF file directly in you C code for the 80x51:

unsigned char acex_ttf[] = {
#include your_project_.ttf
};

This allow you to re-include the TTF each time you compile your project. Then follow the Altera spec and download all the bits & bytes...

Toggle NCONF low then high (follow timing as per spec)
FOR all bits & bytes DO
set the DATA0 bit
toggle DCLK
set the next DATA0 bit
toggle DCLK
...
END FOR
check NSTATUS or CONF_DONE if you want...

If you preprocess your TTF file, you can easily do zero-length coding and reduce the 'code' size, but this will affect your config time.

Have fun!

 

[YUV]

Re: ABOUT CONFIG @ltera ACEX By MicroProcessor & Flas

If you preprocess your TTF file, you can easily do zero-length coding and reduce the 'code' size, but this will affect your config time.

Hi!
You can use small bootloader for uploading TTF file into microcontroller's FLASH. In that case you needn't the recompiling its firmware.
There is one note: the FPGA initialisation time may be significantly long.

 

[edwinni]

dear all:
Now i'm doing the project similar with TERRYWU3's
expecting to get more data about cpld!

 

[lucbra]

Re: ABOUT CONFIG ALTERA ACEX By MicroProcessor & Flas

You can also find some useful information on Lattice's website. They have a reference design using a small CPLD and flash memory to drive the JTAG port.