about comparator threshold

[lhlbluesky]

in pipelined adc(for 1.5-bit-per-stage),if i have designed a bandgap of vref=0.9v(smic0.18um),then how to generate the two reference voltage vref+ and vref-,and if i set vref+=1.4v,vref-=0.4v,is that ok?
if i use resistor ladder to generate the two reference voltage, what's the disadvantage?
anyone can give me some advice,plaese.
thanks first.

 

[A.Anand Srinivasan]

there are some configurations in which you can obtain the reference voltages required by just sizing the comparing CMOS accordingly...

the disadvantage of using resistive ladder is that the power dissipation increases.....