Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

About Clock Tree Synthesis

Status
Not open for further replies.
M

milan.dalwadi

Newbie level 4
Joined
Mar 18, 2013
Messages
5
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,281
Activity points
1,311
How to decide clock skew nd latancy during Clock Tree Synthesis..?

How to meet setup timing in ic compiler from synopsis at CTS stage..??
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top