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About Clock Tree Synthesis

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milan.dalwadi

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How to decide clock skew nd latancy during Clock Tree Synthesis..?

How to meet setup timing in ic compiler from synopsis at CTS stage..??
 

artmalik

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Clock skew and latency can be analysed during the CTS stage by simple handcalculation using the .lib clock buffer delay and wire delay. I think the tools are able to do it very easily. The setup time is done after CTS. I think this is more of a floorplanning issue.
 

milan.dalwadi

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Clock skew and latency can be analysed during the CTS stage by simple handcalculation using the .lib clock buffer delay and wire delay. I think the tools are able to do it very easily. The setup time is done after CTS. I think this is more of a floorplanning issue.

Thanks for ur reply bt how to calculate clock skew and latency using .lib ? Is there any formula for this??
 

artmalik

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no there is no real formula.... Primetime is the tool for these measurement. For hand calculation you can always use the delay of the clock buffer which you are using along with the wireload in the technology you are using. delay_clk_buff+wire_delay for patha and pathb will give some idea as the skew and latency.
 

jigs047

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please explain me about "wire load model".
and where to find this model?

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Generally, the CTS is built by giving the tool minimum targets and try and see what minimum slew & latency the tool is able to achieve.
Having said that one should be careful about the implication of skew and latency on timing. This blog post might help. https://vlsi-soc.blogspot.in/2013/03/clock-skew-implication-on-timing.html


cts is done before routing.so, how to calculate exact delay of each net?
 

rca

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During the synthesis, placement and post placement optimization, the clock is considered as perfect, means, all clocked elements seems the clocks arrived to this pin without any delay, which is not the reality!
The cts step is to have the smallest skew, means the smallest delay with the first flop which received the clock and the latest flop which received the clock.
After this step the hold time will be more easy to fix if the local-skew is better.
It is a trade off between number of buffer on the clock tree and number of buffer on data path to fix hold time.

- - - Updated - - -

During the synthesis, placement and post placement optimization, the clock is considered as perfect, means, all clocked elements seems the clocks arrived to this pin without any delay, which is not the reality!
The cts step is to have the smallest skew, means the smallest delay with the first flop which received the clock and the latest flop which received the clock.
After this step the hold time will be more easy to fix if the local-skew is better.
It is a trade off between number of buffer on the clock tree and number of buffer on data path to fix hold time.
 

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