Clock skew and latency can be analysed during the CTS stage by simple handcalculation using the .lib clock buffer delay and wire delay. I think the tools are able to do it very easily. The setup time is done after CTS. I think this is more of a floorplanning issue.
Generally, the CTS is built by giving the tool minimum targets and try and see what minimum slew & latency the tool is able to achieve.
Having said that one should be careful about the implication of skew and latency on timing. This blog post might help. https://vlsi-soc.blogspot.in/2013/03/clock-skew-implication-on-timing.html