about clock of msp430

[beaver]

msp430 clock

hi guys,

i wrote the following code:
//*************************************
#include <msp430x14x.h>

int main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;

P1DIR=0x01;
P1OUT=0;

while (1)
{
P1OUT^=BIT0;
}

return 0;
}
//**************************************
why the frequency of the square wave from P1.0 is 66K? does it operate by aclk which is 32k? when i changed aclk to 16k,however, the frenquency of that wave became 9.7k. can anybody tell me why and how to set that frequency to a desired one? thanks in advance.

 

[doraemon]

how to set clock frequency in msp430

Hello!

In your code, you don't have any clock set instruction, so the frequency
will be the default (I don't remember if it's ACK or SMCLK, but anyway it will
the clock will have a default value and it will be generated by the internal
DCO). The default frequency is a few 100 kHz.

Now in your code, you have a while loop. Basically it uses 2 instructions in
machine language:
- Invert bit;
- Jump
Each of these will take a few clocks (you can verify in the documentation
how many clocks for each.

For instance, if both instructions take a total of 5 clocks, then the port will
change its state every 5 clocks. Therefore the period of the port signal will
be 10 clocks.
If the default frequency is, say, 600 kHz, then you will get a frequency of
60 kHz. I think it's roughly what you have, and I am not surprised by this value
for the default setting.

But I don't understand what the 9.7 kHz can be. If you use the same loop,
then it means that the CPU runs at a frequency around 100 kHz, so I cannot
tell you if I don't have the exact processor settings.

Dora

Edit after thinking about it: are you sure it's 9.7 k and not 970 hz?
970 Hz would be easily understandable:
- If you set a frequency with the DCO, it's never accurate, so 16 k may be
14 or even less
- Assuming that the 2 instructions XOR and jump take for instance a total
of 7 or 8 clocks for the whole loop, which would mean 14 ~ 16 clocks for one
P1.0 period. If you start with 16 K, you would get something close to 1000 Hz.

hi guys,

i wrote the following code:
//*************************************
#include <msp430x14x.h>

int main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;

P1DIR=0x01;
P1OUT=0;

while (1)
{
P1OUT^=BIT0;
}

return 0;
}
//**************************************
why the frequency of the square wave from P1.0 is 66K? does it operate by aclk which is 32k? when i changed aclk to 16k,however, the frenquency of that wave became 9.7k. can anybody tell me why and how to set that frequency to a desired one? thanks in advance.

 

[beaver]

msp430 change smclk frequency

Hi Dora,

I found a mistake in my code. When I tried to divide ACLK, I wrote

BCSCTL1=DIVA_1;

and this might be the reason for the unexpected 9.7KHz. After I corrected it as

BCSCTL1|=DIVA_1;

the frequency of the square wave from P1.0 remained to be 66KHz. Therefore the output has nothing to do with ACLK in the default mode. And then I divided MCLK and SMCLK in the similiar way and found that the system was operating with MCLK, which is approximately 800KHz.

Still wonder:
1, Why did "BCSCTL1=DIVA_1;" cause such consequence?
2, Where can I get the information about how many clocks each instruction takes?

Thank you!

 

[doraemon]

msp430 set dco frequency

Hello!

Directly to the "still wonder" section.

If you assign DIVA_1 to BCSCTL, it means that you will divide the clock by 2.

Now if you look at the docs, you will read that BCSCTL1 is composed of
- XT2OFF (bit 7, default high)
- XTS (bit 6, default low)
- DIVAx (bits 5 and 4, default low, low)
- XT5V (bit 3, unused)
- RSELx (bits 2, 1, 0, default high, low, low)

So before you changed its value, BCSCTL1 was 10000100
Since you did BCSCTL = DIVA_1 you have replaced it with 00010000
and therefore you have :

- Cleared XT2OFF, which means that the external HF crystal is enabled. If you
have no crystal, I don't know what it does, but it will do it.
- Cleared RSEL2, which means that you have changed the value of the DCO,
setting it to the lowest possible frequency. I think this explains the 9.7 k.

As for the information about how many clocks you need, see the chapter
RISC 16-bit CPU. There are charts for each intstruction / addressing mode
combinations.

Have fun!

Dora.

Hi Dora,

I found a mistake in my code. When I tried to divide ACLK, I wrote

BCSCTL1=DIVA_1;

and this might be the reason for the unexpected 9.7KHz. After I corrected it as

BCSCTL1|=DIVA_1;

the frequency of the square wave from P1.0 remained to be 66KHz. Therefore the output has nothing to do with ACLK in the default mode. And then I divided MCLK and SMCLK in the similiar way and found that the system was operating with MCLK, which is approximately 800KHz.

Still wonder:
1, Why did "BCSCTL1=DIVA_1;" cause such consequence?
2, Where can I get the information about how many clocks each instruction takes?

Thank you!