about clock generation

[kannan2590]

in xilinx 9.1 i have used Single DCM to generate 120 MHZ frequency clock. from this i want to generate 5MHZ , 2.5 MHZ AND again 120 MHZ CLOCKS from this main 120MHZ clock. the raising edges of all the clocks generated should match .IS there any tecjnique in DCM itself so that we can generate 5MHZ , 2.5 MHZ clocks and 120 MHZ so that the raising edges of all the 3 clock generated are at the same instant.

 

[BradtheRad]

Don't know about the equipment you're using, but just to give some kind of answer...

You can count every 24 cycles to generate a 5 MHz clock from 120 MHz. But it will not be easy to keep count of each pulse, while your code is doing other things.

Suppose you were to make a frequency divider from hardware?

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The link below is to a Xilinx discussion about multiplying the frequency. There are likely to be threads about dividers.

http://forums.xilinx.com/t5/Spartan...x-and-4x-clocks-using-a-single-DCM/td-p/15977

 

[barry]

When you say the edges line up at the 'same instant' do you have tolerance? If not, then you are out of luck. Maybe you can explain your requirements in a little more detail. Could you, perhaps, use clock enables that occur at the 2.5 and 5MHz rates and use the 120Mhz clock for you registers?