about cellbased digital backend

[crouch]

After synthesising an rtl verilog to gate level, I use Astro to generate a layout gds file. The gds file passes the DRC checking, but I cannot get a circuit level netlist or schematic to run LVS/LPE checking.

Questions are:
1.Is there needs to run LVS/LPE checking for cellbased design?
2.If there is, how can I get the circuit level netlist

thanks

 

[leeenghan]

Hi,

The last time I use Calibre, there is a command to translate Verilog to something very close to Spice. This is then use for LVS. Cannot remember the name of the command, but it is documented in the manual.

It is the same for Hercules. Not sure about Assura.

Regards,
Eng Han
www.eda-utilities.com

 

[fago]

Using Astro to dump out gate level netlist, then traslate this netlist to spice by the command v2lvs in Calibre

 

[crouch]

hi fago

i can get the gate level netlist,
but netlist translated from the layout
is a circuit level one.
the lvs checking fails, how to get the circuit level
netlist from astro or get level netlist from layout?

thank you

 

[fago]

If you use Astro, you can follow this way:
"cell->Repare Hierarchy Information", then
"cell->Hierarchy Verilog(netlist?) Out",
after that, you will get a gate level netlist.
Using Calibre command "v2lvs -v xx.v -o .xxx.spi", you will get spice netlist. Modify this netlist about power and ground information according your requirement, something like "GLOBAL VDD,VSS........, or .CONNECT VDD XX". Also, don't forget include those library spice netlist.

 

[crouch]

thank you
i'll try it out later and tell you whether it works

 

[crouch]

yes, it works!
and I think for a digital circuit, lpe is a too huge work to do, so just do post_layout simulation with sdf(generated by primetime with astro's sdc output).
Am I right?

 

[semi_jl]

You can do it in this way, but running LPE will be better!