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About behavior modelling of ADC

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VINAY_RAO

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In behavior modelling of flash ADC,by simulating the idea of architecture ,is it possible to predict the resulting sampling frequency of the ADC???.
We need to include real time delays while simulating to anticipate the sampling rate for the architecture we selected??
 

It would just be as good as a guess. My suggestion is that you try a quick design of the most critical blocks and see what you get.
 

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