About asynchronous FIFO and dual-port SRAM

[vtmc]

Once in an interview, I said I know some concept of asyn FIFO, and was asked to explain. I drew the block diagram and before I started blah blah about how to control under/overflow, the interviewer said, "Stop, how U design the dual-port SRAM? That's the most difficult part.".

I was so surprised because I never knew that's the most important part. I didn't take any course about asyn FIFO. All I did is to google some papers on this topic, and then read some HDL examples. In all these examples, the SRAM is presented with a few lines of HDL and is a very simple block.

My question is, as self-study, what kind of resourse or methodology can help me with this kind of pitfall? This may seem pretty obvious for those in the industry but not for me, a 3 months to graduate MS student.

Thank you for the help.

 

[ljxpjpjljx]

search this forum to get the information!

 

[prashanthknl]

Check out that link to know about the RAM or else search Verilog HDL by Samir Palnitkar Book for that
https://www.asic-world.com/examples/verilog/ram_dp_sr_sw.html

 

[salma ali bakr]

don't expect to know all the hints and tricks of design during your studies or even your self studying!! you'll take time to get this knowledge...and it'll build up through the years...

for now, just try to read a lot...take info about one design from different resources...read blogs and advice of experienced engineers about the tips of design...

one of the best blogs i recommend is:

https://asicdigitaldesign.wordpress.com/

i'm currently designing a FIFO, and i see that the most important part is the controller not the RAM...unlike your interviewer!!..so people have different opinions too...what's yours ??

 

[Nir Dahan]

one of the best blogs i recommend is:

https://asicdigitaldesign.wordpress.com/

thanks for the compliments...

I will run a new post soon on dual port SRAMs so stay tuned.

ND
https://asicdigitaldesign.wordpress.com/

 

[salma ali bakr]

WOW...it's you
I love your blog...

Thank you...

 

[cheelgo]

the blog is quite good! waiting for your post update!

 

[vtmc]

Hi,

Thank you all for the help. Guess you are right with the multiple sources of learning and thanks for recommending the websites.

BTW, the guy is a principle engr at Qualcomm, so I guess he may be seeing things in a different point of view...I dont know. The interviewers are all nice, but the process sucks cuz I screwed up T_T