Abel language problem

[Revanth Machineni]

HELLO, I WANT SOME EXPLANATION OF THIS EQUATION ![q1,q0] := (![q1,q0].FB + 1) & !reset;. I JUST WANT TO KNOW WHAT [q1,q0].FB WILL GET OUTPUT AND JUST CAN ANY ONE GIVE SOME EXPALNATION ON THIS. AND ACTUALLY I AM NOT UNDERSTANDING WHAT THIS FEEDBACK REGISTOR WILL GET INPUT.

HOPE ANY1 WILL SOLVE MY PROBLEM

 

[std_match]

It seems to be a 2-bit counter with reset.

In the CPLD's, each register is normally associated with a pin.
[q1,q0] gives the current value at the pins.
[q1,q0].FB gives the current output at the internal register. This is much faster, so the timing will be better. It also works even if the associated pins are used as inputs.

 

[Revanth Machineni]

can i know what r the thinks involved in FPGA.Presently i am working on pal16v8, and is it ok to go with ABEL HDL or is it better to shift to VHDL.

It seems to be a 2-bit counter with reset.

In the CPLD's, each register is normally associated with a pin.
[q1,q0] gives the current value at the pins.
[q1,q0].FB gives the current output at the internal register. This is much faster, so the timing will be better. It also works even if the associated pins are used as inputs.