Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

A Way to simulate the PLL jitter with HSPICE

Status
Not open for further replies.
A

asicpark

Member level 1
Member level 1
Joined
May 14, 2004
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
273
Hi all,

I'm wondering how I can simulate the PLL jitter with HSPICE.
I've just thought the FTT thing, but it might be a good way.
If anyone who knows the way, please tell me.

Thanks in advance.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top