a warning about design compile: fanout

[iamczx]

Warning: Design 'top' contains 2 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)

How to eliminate this warning?
use command set_max_fanout?

thanks in advance

 

[henrik2000]

May be you're trying to drive to many entites with one single signal. try to share.. As you don't give a lot of details on the tool set used, or the language either it's really difficult to help you

 

[jankin]

maybe you should look for the net.

 

[iamczx]

I use verilog . When I compile the "top ", I set the clk and the rst signal as ideal network.
So ,the high fan-out net won't be clk and rst net,is it?

And , is there any command to find the hign fanout net ?