a truth table question (use output as one of the input for a gate)

[bhl777]

For example, if we have a OR gate, one input depends on us and the other input is like the feedback from the output, how can we generate the truth table? Thank you!

 

[andre_luis]

OUT <= OUT | IN

Seems to be strictly a sequential logic statement, not combinational.

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[dhaval4987]

If it starts from initial state and say Controlled input is 0= then output will be latched to 0. Because the controlled input is 0 and the fed back value is also 0. There is no way the fed back value could be set to 1 without changing the controlled input.

Once you set control input to 1- no matter what the feedback it- it will latch to 1 for ever.

Are you looking to make a latch?

 

[bhl777]

Hi dhaval4987, thank you for your explanation! I am just doing some execises and found this problem. So it means we can write down the truth table like this:
Input Output(also the other input)'
0 0
1 1
Is it correct? Becasue I am thinking about that if the input is 0, the output can be 1 because 0(OR)1=1, should I write the truth table as
Input Output(also the other input)'
0 0
0 1
1 1
? Please advise!

If it starts from initial state and say Controlled input is 0= then output will be latched to 0. Because the controlled input is 0 and the fed back value is also 0. There is no way the fed back value could be set to 1 without changing the controlled input.

Once you set control input to 1- no matter what the feedback it- it will latch to 1 for ever.

Are you looking to make a latch?

 

[andre_luis]

Y US OUT
1 1 x
1 0 1

According dhaval analysis ( If I´m no wrong ).

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[dhaval4987]

Controlled Fed back Out
0 0 0
0 1 1 : This case is invalid in the beginning when Controlled lines do not change. Coz how will output change if Controlled input is 0!? Do you get what I mean?
Once the controlled input is set to 1 then output will be 1 for rest of the cases, even if you switch the controlled line to 0. (The case above becomes realistic).

 

[bhl777]

Hi Andre,thank you for your reply! But I am still not sure from your statement, whenY=1, US=1, why OUT=X? This is an OR gate and Y equals to OUT, could you give me some more guidance?

According dhaval analysis ( If I´m no wrong ).

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[dhaval4987]

yes andre is correct... this is sequential design and cant be explained by combinational approach.

 

[bhl777]

Yes I got you! So I should make a statement to say that once Controlled is 1, the output will be 1 and even if Controlled changed back to 0, the output is still 1, am I right?

Controlled Fed back Out
0 0 0
0 1 1 : This case is invalid in the beginning when Controlled lines do not change. Coz how will output change if Controlled input is 0!? Do you get what I mean?
Once the controlled input is set to 1 then output will be 1 for rest of the cases, even if you switch the controlled line to 0. (The case above becomes realistic).

 

[dhaval4987]

yes. you are. are you trying to design an latch or FF???

 

[andre_luis]

...Y equals to OUT...

Not in time domain, because is latched.

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[bhl777]

OK I got Andre too. So for sequential design how can we write the truth table?

yes andre is correct... this is sequential design and cant be explained by combinational approach.

---------- Post added at 01:23 ---------- Previous post was at 01:20 ----------

Not a exact design, actualluy I am doing a problem of a book and found this interesting.

yes. you are. are you trying to design an latch or FF???

 

[dhaval4987]

Output depends on Previous State and Present Input. you can find about it in almost all basic books or on google. pretty easy to understand.

 

[bhl777]

Sorry Andre I am still a little bit confused. Could you tell me more about this?
Y US OUT
1 1 x
1 0 1
From here you said even if there is a wire (or connection) between the output and Y, it is still possibel that Y=1. US=1 and OUT=0 because it is latched?

Not in time domain, because is latched.

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---------- Post added at 01:35 ---------- Previous post was at 01:31 ----------

Yes I know this. So you are saying that now the truth table should be written according to time but not combination? If it is true, could you tell me how?

Output depends on Previous State and Present Input. you can find about it in almost all basic books or on google. pretty easy to understand.

 

[dhaval4987]

you can read the truth table like this:

If the Previous State was X and the Present Input is Y then Next State becomes Z.

For the next entry in Truth Table- you should use Z as 'Previous State'.

I hope this helps.

 

[andre_luis]

Maybe a better way to analyse be not by truth table, but with state machine.
If I´m not wrong, that´s the behaviour using a D flip-flop :

**broken link removed**

Wich confirms a infinite loop after certain state, like predicted by dhaval.

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