A synthesis problem about Design Compiler

[cyteng]

design compiler naming rule

After synthesis and optimization of my verilog file, I find some net( or wire) names is very strange. For example , the net connected from the output of nor gate to the data input of D flip-flop is called
" *cell*11/U2/control ". But I want very short net name like " N100" .
Does anyone know the answer to this question ?




Cyteng

 

[buzkiller]

design compiler naming rules

May be you should flatten your hierarchies.

regards,
Buzkiller.

 

[cuiyujie]

design compiler net name

You cannot make sure all the name of all your internal wires is the same as before, adapt to these changes and don't count on post simulation a lot in verification.

 

[cdic]

ungroup naming rule design compiler

Change naming rule, eliminate *cell*, it's not fit for back-end design, also make sure no \ exist.

 

[magicball]

design compier changing cell names

There are several articles in Solv*Net, the common solution is change names after synthesis.

 

[cyteng]

design compiler synthesis

If I would like to change the net name *cell*11/U2/CONTROL1 to NCONTROL1 , how do I write define_name_rulse command ?

I use "define_name_rules myrule -map {{"\*cell\*","U"}}",
but it maps "*cell*11/U2/CONTROL1" to "U".

 

[andromeda]

09 dc compiler + define_name_rules

The simplest way is to use:
ungroup -flatten all -simple_names
(of course, if you want to remove the hierarchy)
Switch -simple_names will give you this type of names

 

[joe2moon]

design compiler change net name

I think you need to define the naming rule for "simple_names" before you can use it in change naming command

 

[wllee]

synthesis bug

I hear DC2002.05 has bug in change naming rule function.
Maybe this is the bug.

 

[cnz]

how to use define_name_rules

Change naming rule, eliminate *cell*, it's not fit for back-end design, also make sure no \ exist.

I think that if you use cadence SE , we must eliminate "\".
however, to "*cell*" we needn't do it !

 

[cnz]

design compiler net names

define_name_rules BORG -allowed {A-Z a-z 0-9 _} \
-first_restricted {_ 0-9} \
-type cell

define_name_rules BORG -allowed {A-Z a-z 0-9 [ ] _} \
-first_restricted {_ 0-9} \
-type port

define_name_rules BORG -allowed {A-Z a-z 0-9 _} \
-first_restricted {_ 0-9} \
-type net

define_name_rules BORG -target_bus_naming_style {%s_%d} \
-type net

set bus_naming_style %s_%d

define_name_rules BORG -case_insensitive \
-map { {{"*cell*", "U"},{"*-return", "RET"}} }


change_names -hier -rule BORG