a strange thing met when I use dc

[xv_ning999]

during synthensis of my design, I find a strange thing in my timing report . No matter how I specify my clock duty cycle.My DC always report that the result of worst timing path is exactly the same as my clock cycle. For example if I set my clock to be 20ns, it report that the worst path in this clock domain is 20ns, then I set the cycle to be 10ns, it also report that the worst path in this clock domain is 10ns.So I am confused .Is something wrong in my design or my synthesis script . Could anyone give some advice ? thanks

 

[eda_wiz]

post your design and script so that others can give comments

 

[xv_ning999]

my design has about 1m gates and my script is more than 500 lines. so it can not be post here.I can only say that every time the critical path is the same ,I an confuse about it ,did anyone meet this problem before please help

 

[leeenghan]

Hi,

I think if you look at the timing path report it will become clear.

Regards,
Eng Han
www.eda-utilities.com

 

[jjww110]

it seems strange ,please show you timing report and constrain file , or we can not help u!!

 

[yuenkit]

copy and paste the content of report_timing here.