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A strange ERROR when using Virtex7

Sunshine_accu

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To all professionals,
I am new to FPGA design and have tried all my best to solve the error, but it still turned to be a failure. Therefore, I post to obtain some guidance, hopefully.

In detail, I instantiate module wgn_noise for two times and obtain two output signals—wgn_noise_I and wgn_noise_Q(all 9 bits).
Strange is that the highest four bits of signal wgn_noise_Q are CORRECT. But the highest two bits of signal wgn_noise_I are always '1', and bit6 and bit5 are always opposite.The exact error are in the following screenshot.

The function of the module is to add AWGN nosie to input signal and is a tiny part of the whole project. In addition, the whole project works at 160M frequency and the timing is meeting requirement(No timin errors are reported).

定时问题.png
 

niciki

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It is hard to say what is wrong without shown the input signal and the added noise values. Give more details: show us your HDL design and/or full signals scope.
 

Sunshine_accu

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It is hard to say what is wrong without shown the input signal and the added noise values. Give more details: show us your HDL design and/or full signals scope.
Thank you very much for the reply. The attached file is the source design of module wgn.v.
The signal noise_I corresponds to the scene wher input state[1:0]="00", where noise_Q when input state[1:0]="10".
Next is the exact waveform I watched from Chipscope.

噪声波形2.JPG
 

Attachments

  • module_wgn.zip
    2.8 KB · Views: 7

FvM

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When you say the problem is related to Virtex 7, do I understand right that the reported behavior (some noise generator bits not toggling) is only observed in synthesis but not in simulation?

Could it be that some noise generator bits are discarded by the synthesis tool because they are unconnected in the design?
 

Sunshine_accu

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When you say the problem is related to Virtex 7, do I understand right that the reported behavior (some noise generator bits not toggling) is only observed in synthesis but not in simulation?

Could it be that some noise generator bits are discarded by the synthesis tool because they are unconnected in the design?
Maybe it could be one of the reason, but please, how could I judge which bits are unconnected in the design?
Thanks a lot, hope your reply~
 

KlausST

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Hi,

Currently only you know what HDL code you have written and which bits are used or not.

Thus niciki in post#2 asked for your code. You still hide it. This makes it difficult to help.

An example:
Your car does not work. You contact your garage and send an audio file with the noise your car makes during starting.
So the garage just is able to hear the symptom, but is not able to do real tests on the car...to find the root cause.

Klaus
 
Last edited:

FvM

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The application conditions aren't yet clear. You have posted the noise generator module code, it's working apparently correctly in functional simulation. I'd expect timing closure up to 200 MHz with performance FPGA like Virtex.

But we don't what are the conditions to bring up the reported erroneous behavior, neither which tests you performed to isolate the problem, e.g. reducing the clock frequency, instantiate the module in a different top design.
 

niciki

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I have viewed wgn.v file from post #3 and I have got a question - is it a product of some kind a high level synthesis tool, because this file is hard for me to read and understand?
250 bit for state?!
 

FvM

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is it a product of some kind a high level synthesis tool, because this file is hard for me to read and understand?
250 bit for state?!
I admit that it's impossible to read out the underlying algorithm of this code, the OP owes an explanation. But related to the reported problems, the exact generation algorithm is irrelevant. We have some kind of finite state machine characterized by the number of state bits and the maximal register-to-register delay achieved in synthesis.
 

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