a simple question for OTA step response configuration

[ethan]

output stage current ota

hello everybody,

I got a question for the step response configuration, which I have not thought about clearly.

My opamp is single stage fully differential fold-cascode OTA to drive capactive load. The CMFB is switch capacitor circuit.

When I tried to test step response, I used unity gain feedback configuration (shown in figure (a)) and got expected results. Since, in reality, this OTA need to work with two phase clocks for both SC-CMFB and close-loop configuration, I used figure (b) to test it with clock phase 1 (and both p1 and p2 for internal SC-CMFB with same frequency and non-overlapping). But it seems something wrong here and I couldn't get expected results. The output Vop and Vom are keeping constants in certain values. There is no ramp or slew behavior for the outputs.


So, what's wrong with configuration (b)? Is configuration (c) correct for step response? or other configuration for this step response?

Note: all capacitors are same values and all resistors are greater than 100Mohms.
phase 1 is the resetable phase; phase 2 is the amplification phase.

Appreciate your suggestion.

ethan

 

[ethan]

step response ota

Another question always bother me is that I couldn't get the expected slew rate from simulation (comparing with SR calculation).

Say, in this fully-differential single stage fold-cascode OPAMP with PMOS input diff-pair,
the DC current of each side of the output stage is set to 150uA,
Cload=5pF,
the Ibias of tail current source in the input stage is 400uA,

then the calculated SR by using the output stage current is 150uA/5pF=30v/us.

(For fully differential fold-cascode structure, there are two different slew rate values depending to whether output is being charged or discharged. In this case, the SR calculation for output charging Cload is a little bit smaller than the case of discharging Cload, in which SR is 200uA/5pF=40v/us.)
please correct me if I am wrong.


Then by using configuration (a) above and setting differential large signal inputs step from 0.5v to 4.5v (in order to let all transistors within saturation, the rising time and falling time of pulse are 25ps) with 5v VDD, I can get each output slews from 0.51v to 4.49v (or reverse).

But when I use the SR function in the calculator from Cadence Analog Design Envn to measure that slew period, I only can get at most 20v/us on each single output, not even close to 30v/us.

I have read many papers and books (John & Martin, etc), most of the authors claimed the SR of their OPAMPs from the step response plots.

One of my colleagues told me that the measured SR is signal SR from waveform, not opamp slew rate. if there is no slew rate limitation in the opamp. then that's fine. Is he right?

But, if this is the case which is based on what he said, no SR limitation, then I can never get that 30v/us SR from simulation. Is that right?

please help me.

ethan

 

[Humungus]

john&martin ota

When calculating SR, you must consider internal and external SR. Remember that for your output transistors to swing, their gates must be swung too. So you must also see at the change rate of the gate of the output transistors when driven by the current of the input stage.

 

[ethan]

fold cascode ota slew

When calculating SR, you must consider internal and external SR. Remember that for your output transistors to swing, their gates must be swung too. So you must also see at the change rate of the gate of the output transistors when driven by the current of the input stage.

Thanks for your reply. But I am not quite understanding with "change rate of the gate of the output transistors". for this one stage fold-cascode opamp, there are four transistors in each side of the output stage, you mean the cascode transistors? or observe the gate swing of the input differ-pair?

And also how can I measure the internal SR?

Another question is normally how large step pulse signal you apply for step response?
one case, say, is to apply the pulse with 0 to VDD step and then there must be some transistors in triode resgion under this senario"
or only apply several hundreds of mili-volts step pulse to see the step response?

which way is used to measure SR from simulation output SR?

Thanks again

ethan