A question on flip-flops

[rakko]

Does anyone know why in a flip-flop only setup is effected by clock speed but not hold? It seems to me that both setup and hold should be a fuction of clock speed. For example if the setup requirement = hold requirement = 1 nS in a FF, then, if the clock frequency is swepped from 500 MHz to 2 GHz, at 1 GHz or greater both setup and holds are going to be violated since the clock period will be shorter than setup/hold requirement of the flip flop. Doesn't this prove that they are both a function of frequency??

 

[randyest]

Setup is not affected by clock speed. Setup for a given flop type is a function of the flop's design and the process it's made in. Setup values are in the library. Setup can be affected by input slew rate and output load of the flop, but not the clock frequency.

Setup does affect the allowable time difference between two clock edges: the launch edge and the capture edge. So setup subtracts from the max possible clock rate.

Hold is also not affected by clock speed. Like setup, hold for a given flop type is a function of the flop's design and the process it's made in. Hold values are in the library. Hold can be affected by input slew rate and output load of the flop, but not the clock frequency.

The difference is that hold is related to only one clock edge, the capture edge (relative to the data.) It doesn't matter how long ago the launch edge hit, the hold time at the capture flop is always the same.

So increasing hold time requirement doesn't directly subtract from max clock speed. But at some ridiculously high speed it is indeed impossible to meet both setup and hold, as in your example. But that doesn't prove that either setup or hold are a function of clock frequency, because neither depend on clock frequency as I explained above. If you doubt it, look in your .lib file and see.

I hope that helps clear up your confusion.

edit: also, note that hold time is how long DATA must be stable after the clock edge. So you could have a FF with 1ns hold time requirement and a 2GHz clock and, as long as DATA was a constant it would work fine Same with setup really.

 

[rakko]

Thanks for the reply but I'm not sure about your last edit. If the data is constant and not changing there be no need to FF in the 1st place. Otherwise, If the hold time requirement is 1nS this means the 1st latch can not close sooner than 1nS but the 2GHz clock forces it to close 250pS after the rising edge and this violates hold on the 1st FF latch.

I read your post a couple of times and think I understand why setup needs 2 clock edges and hold only one clock to do its calculations; For the timing tool to calculate setup or hold, it needs a fixed point in time (clock edge) and a data transition. It uses the time it takes from the clock edge to the 1st transition on the data to calculate setup. Since hold happens after the capture edge, it can use the time from that edge to next data transition to see if hold was satisfied. My point is that the clock edge always has to come before the transition of the data or otherwise it be very difficult to know when to start the calculations. This must be why setup uses the launching edge of the clock and hold uses the capture edge. Or is it...

 

[randyest]

Thanks for the reply but I'm not sure about your last edit. If the data is constant and not changing there be no need to FF in the 1st place. Otherwise, If the hold time requirement is 1nS this means the 1st latch can not close sooner than 1nS but the 2GHz clock forces it to close 250pS after the rising edge and this violates hold on the 1st FF latch.

Well that's not totally true. You might want to have a FF (a retention FF) if the data source was in a voltage island that would be powered down sometimes, but you want to hold the value from it, and you don't have isolation cells available But I admit I'm just being pedantic and kind of silly with that edit.

But the fact is that neither setup nor hold are a function of frequency in any way. Maybe you mean the converse: that max freq is a function of setup and/or hold? If so, yes, max freq depends on setup in that setup subtracts from the clock period that is available to send data from one flop to the next. The larger your setup time, the fewer gates/delays you can have between flops for a given clock freq. But max freq does not depend on hold in the same way. Max freq doesn't depend on hold at all until you get to the extreme case where period < hold time as in your example. Until that point, more gates/delays between flops actually makes it easier to meet hold time, which is opposite from setup.

I read your post a couple of times and think I understand why setup needs 2 clock edges and hold only one clock to do its calculations; For the timing tool to calculate setup or hold, it needs a fixed point in time (clock edge) and a data transition. It uses the time it takes from the clock edge to the 1st transition on the data to calculate setup. Since hold happens after the capture edge, it can use the time from that edge to next data transition to see if hold was satisfied.

I think you understand this part right.

My point is that the clock edge always has to come before the transition of the data or otherwise it be very difficult to know when to start the calculations. This must be why setup uses the launching edge of the clock and hold uses the capture edge. Or is it...

This isn't correct, I don't think. The data transition almost always occurs before the clock edge (earlier by at least the setup time) and stays stable after the clock edge (by at least hold time.) Then the data changes before the next clock edge. Is that what you mean? Sorry but it's not clear to me where your confusion is here.

Also, there are such things as negative-hold flops which allow data to change before the clock edge and still capture the data OK.

 

[supercat]

But max freq does not depend on hold in the same way.

Unless setup time was turned into hold time by delaying the clock, which will in turn increase the register's effective propagation delay.

My point is that the clock edge always has to come before the transition of the data or otherwise it be very difficult to know when to start the calculations. This must be why setup uses the launching edge of the clock and hold uses the capture edge. Or is it...

This isn't correct, I don't think. The data transition almost always occurs before the clock edge (earlier by at least the setup time) and stays stable after the clock edge (by at least hold time.) Then the data changes before the next clock edge. Is that what you mean? Sorry but it's not clear to me where your confusion is here.

I think Rakko's point was that to know whether the setup constraint is met on a given clock edge, one must measure the data propagation time from the previous clock edge.

Also, there are such things as negative-hold flops which allow data to change before the clock edge and still capture the data OK.

Sure. One can make a negative-hold register by delaying the data, or make a negative-setup register by delaying the clock. Either may be useful if externally-supplied clock and data signals are expected to change simultaneously.