a question about "-sverilog" option of vcs

[xiaojigao]

I have an RTL design(suppose it's name is dut.v) which is writen in verilog, and a testbench(suppose it's name is tb.sv) which is writen in systemverilog. When I simulate my RTL using vcs, I add "-sverilog" option to support systemverilog. But I find a problem: vcs will compile both dut.v and tb.sv as systemverilog. This is not what I wanted.
I hope vcs compiling dut.v as verilog, and compiling tb.sv as systemverilog. How can I achieve my goal ? Is there any options to tell vcs "just compile files as their file extensions"? i.e. compile *.v file as verilog, and compile *.sv as systemverilog. I know irun(cadence EDA tool) can do this. But I don't know how to tell vcs do this. If I remove "-sverilog" option, it will compile all files as verilog and will report compile error when compile tb.sv.

Then I will explain why I want vcs to compile dut.v as verilog.
If there are below lines of code in dut.v:
reg aa;
assign aa = sel ? bb : cc;

Actually these code is not correct, below aa should be decleared as wire, but not reg. But, if this file is compiled as systemverilog, it will not report error. This is not what I wanted.
(I wonder if these code can be synthesised correctly and will not report error?)

Thanks very much!