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A question about imput impedence

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simbaliya

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I was asked some basic questions during a interview, there is one question I can not answer, anybody can help me on this?
Q2.jpg
 

To a first approximation, if the beta is very large than the transistor will sink all the input current with negligible change in input voltage, thus Rin will be zero.
 

I think it's trickier than that, Zapper. You're ignoring the effect of the left transistor.

My analysis would be as follows:
Firstly, assume matched transistors, so the collector current of the two transistors is equal.

Let's say both resistors are 1K in value and the voltage on the right transistors collector is raised 10mV.

10uA will flow through the right transistor to the transistors' bases. This will tend to turn them both on harder. This causes the left transistor's collector voltage to drop, so current will flow from the bases through the left resistor to the left transistor's collector.

Equilibrium is reached when the voltage at the left transistor's collecter has dropped by 10mV, so that the current flowing out of the bases through the left resistor cancels the current flowing into the bases through the right resistor, leaving no net base current.

Since the current through the left transistor has increased by 10uA, the current through the right transistor must also have increased by 10uA. Thus the total current flowing into the external node connected to the right transistor's collector is 20uA.

The input impedance is thus 10mV/20uA = 500 Ohms = R/2

[Belatedly realises a picture is worth a thousand words - I'll draw something and post it soon]

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To a first approximation, assuming ideal transistors etc:

 

It's certainly true that the current-mirror has an effect, which I incorrectly didn't include in my simple analysis. But I did a couple simulations with a high gain transistor and your circuit values, and It seems to be performing differently than suggested. I added a switch between them so, in the first half of the simulation (0-1ms) the switch is open, and the current mirror has no effect. In the second half of the simulation (1ms-2ms) the switch is closed and the current mirror is connected.

The 1st is with a maximum input current of 20µA. The input resistance is not much different in either case with the input impedance going from 31.6kΩ to 32.1kΩ.

The 2nd is with a maximum input current of 1mA. Now the input resistance varies from 653Ω to 1.13kΩ with the mirror unconnected and connected respectively.

In either case the input impedance goes down as the input current goes up. So it's not clear to me what the correct answer to the OPs question is. :?:

Mirror 1.gifMirror 2.gif
 

Hi Zapper

I assumed that the input impedance in question was delta V / delta I, rather than absolute V / absolute I. I'm not sure what the corrrect terminology is.

In your first test, with the switch closed, Vin rose 10mV from 632mV to 642mV as Iin increased from zero to 20uA. Thus input impedance = 10mV / 20uA = 500Ω as predicted.

Similarly, in your second test, Vin rose by about 0.5V when Iin changed by 1mA, again giving Zin = 500Ω (0.5V / 1mA)
 

Question is pure theoretical. Input impedance equation should be solved using four-pole parameters of transistor. Expression is needed and not numerical result.
 

Hi Zapper

I assumed that the input impedance in question was delta V / delta I, rather than absolute V / absolute I. I'm not sure what the corrrect terminology is.

In your first test, with the switch closed, Vin rose 10mV from 632mV to 642mV as Iin increased from zero to 20uA. Thus input impedance = 10mV / 20uA = 500Ω as predicted.

Similarly, in your second test, Vin rose by about 0.5V when Iin changed by 1mA, again giving Zin = 500Ω (0.5V / 1mA)
I agree with your analysis. The question was likely referring to the dynamic impedance which is indeed 1/2 R (as long as the input current is below the collector constant current source. Above that current the current-mirror no longer operates and the dynamic impedance will be reduced).
 

Hi guys,
here some my thoughts about it:
1. If beta very hight, then base currents very low ~ 0.
2. Let's do small-signal circuit and calculate Rin:
check my attachment ^)
3. Assuming gm ~ inf, equal Rin reduces to R/2
 

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  • Rin.jpg
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I was asked some basic questions during a interview, there is one question I can not answer, anybody can help me on this?
View attachment 100679

The input impedance is the source voltage divided by the source current when the other active sources and sinks are replaced by their respective impedances. That means disconnecting the two current sources in the collector circuits. I am assuming Vbe is zero. So, the source current contributed by the right transistor is beta *(Vs/R). The same for the left transistor. That makes the total source current Is =2*(beta *(Vs/R)) . Therefore, the input impedance Vs/Is = R/(2*beta), a very low value indeed when the beta is high.

Ratch
 

I am assuming Vbe is zero. So, the source current contributed by the right transistor is beta *(Vs/R). [/B], a very low value indeed when the beta is high.

Ratch
If Vbe is zero, there no currents in transistors...
 

If Vbe is zero, there no currents in transistors...

Since I am looking at the change in voltage (Vs) divided by the change in current (Is), I can ignore the relatively constant Vbe in my calculations.

Ratch
 

The input impedance is the source voltage divided by the source current when the other active sources and sinks are replaced by their respective impedances. That means disconnecting the two current sources in the collector circuits. I am assuming Vbe is zero. So, the source current contributed by the right transistor is beta *(Vs/R). The same for the left transistor. That makes the total source current Is =2*(beta *(Vs/R)) . Therefore, the input impedance Vs/Is = R/(2*beta), a very low value indeed when the beta is high.

Ratch
I'm greatly surprised at your conclusion. :shock: You are always going on about how BJT transistors are voltage operated devices and not current operated and yet here you are, assuming that Vbe = 0. Even an ideal transistor does not have that characteristic, even with infinite beta, since that means they would not operate as current mirrors, which is what this circuit is. Current mirrors, as I'm sure you know, depend upon the transconductance of the BJT for operation. So if you add in the normal Vbe then you will find that the dynamic input impedance is R/2 as I simulated, and sarge and godfreyl calculated.
 
Since I am looking at the change in voltage (Vs) divided by the change in current (Is), I can ignore the relatively constant Vbe in my calculations.

Ratch
You ignore vbe, but don't ignore base current (Rbe=beta/gm)...
Anyway, you can check our calculations and say for us where we wrong.
 

I'm greatly surprised at your conclusion. :shock: You are always going on about how BJT transistors are voltage operated devices and not current operated and yet here you are, assuming that Vbe = 0. Even an ideal transistor does not have that characteristic, even with infinite beta, since that means they would not operate as current mirrors, which is what this circuit is. Current mirrors, as I'm sure you know, depend upon the transconductance of the BJT for operation. So if you add in the normal Vbe then you will find that the dynamic input impedance is R/2 as I simulated, and sarge and godfreyl calculated.

Why are you surprised? I am just following the definition for dynamic input impedance. That being the change in Vs divided by the change in Is. Since Vbe is constant in the active region, especially with constant collector current, the change in Is is determined solely by the change in Vs, and Vbe can be ignored. This does not conflict with my believe that a BJT is a transconductance device, or whether the circuit is a current mirror. Adding the constant Vbe voltage to the dynamic impedance calculation will guarantee a wrong answer. Ratch

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You ignore vbe, but don't ignore base current (Rbe=beta/gm)...

It depends. If you want to take Rbe into consideration, then the dynamic input impedance is (R+Rbe)/(2*beta). If Rbe is small compared to R, then it doesn't matter too much.

Anyway, you can check our calculations and say for us where we wrong.

Better yet, you can check my calculation since it is simpler. Tell me where I went off track.

Ratch
 

Better yet, you can check my calculation since it is simpler. Tell me where I went off track.
Right here:
So, the source current contributed by the right transistor is beta *(Vs/R)
You are assuming that the base current of the right transistor = Vs/R but that's not true.

Vbe of both transistors is the same. Thus their collector currents are the same. The collector current of the left transistor flows through the left resistor from the transistor bases, cancelling most of the current flowing to the bases through the right resistor.
 
Last edited:

Cadence virtuoso agree with us even with real transistors:
 

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  • OutputResistancePlot.png
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Right here:

You are assuming that the base current of the right transistor = Vs/R but that's not true.

Vbe of both transistors is the same. Thus their collector currents are the same. The collector current of the left transistor flows through the left resistor from the transistor bases, cancelling most of the current flowing to the bases through the right resistor.

Yes, I see you are correct. The current in the left transistor skews the voltage at the junction of the the two R's. I did a node calculation which I won't publish here unless someone wants to see it. I did get the same result you did of R/2.

Ratch
 

Move it up a notch. The driving point resistance at either collector is R/2. One might then think that the differential resistance between collectors is R; is it?
 

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