A question about fully-diff folded-cascode with sc-cmfb

[Alan_Nesta]

3.3v vdd
presim ac and cmfb are both ok
ac gain=75dB
cmfb gain=70dB
dc operation node OK cm-output=1.65v
but when do c-only postsim
gain is still large
ac=73dB
cmfb=65dB
but cm output voltage is 1.5v!
why?
the op is p-input pair single stage
cmfb connect to p-load of the cascode op

 

[PaloAlto]

You do a C-only DC OP simulation and vcm is wrong? That shouldn't be the case. C-only is just adding capacitors to your circuit, so, no DC information. What else is changing from one sim to the other? Try to simplify things and post the differences, there should be something more than just the new Cs.

You can also do instead of C-only a lvs-extracted view and see what you get

 

[Alan_Nesta]

I've found the reason!
sa sb is large!
I only know the parameter as ad ps pd
what is sa sb?

 

[pbs681]

I've found the reason!
sa sb is large!
I only know the parameter as ad ps pd
what is sa sb?

sa and sb is a stress effect parameter. It will affect your Id. Transistor 0.18um and below experience this effect. Just google stress effect u will get a detail explanation. I believe u are using BSIM3. If u r using BSIM4, u will 1 more extra parameter for stress which is sd.....

 

[Alan_Nesta]

in layout how to decrease sa sb?

 

[JoannesPaulus]

You can't decrease sa and sb, they are a physical dimension of the transistor but you can group the devices so that their sa and sb match.

 

[pbs681]

in layout how to decrease sa sb?

sa and sb in term of phisical meaning is a distance from the edge of active (STI) in x-dir to the poly. This distance has minimum requirement in Design Rule, but if ur current transistor is bigger than minimum, u can always reduce it....

or maybe ur extracted netlist has problem with extracted sa and sb. Cjheck ur extracted netlist (unit and order)

 

[Alan_Nesta]

sa sb is about 3-5e-6
is it too large for 90nm process?
my presim set the parameter about 5e-7

 

[pbs681]

sa sb is about 3-5e-6
is it too large for 90nm process?
my presim set the parameter about 5e-7

normal value shud be 5e-7.... check ur layout....

 

[Alan_Nesta]

how to check?
I mean how to decrease this parameter in layout?

 

[pbs681]

how to check?
I mean how to decrease this parameter in layout?

see page 19 of this document: http://www.cdnusers.org/community/virtuoso/resources/ctp_CDNLive2005_1421_Strang.pdf

 

[Alan_Nesta]

I've seen it
but it says sa sb are better when large
really?
my presim shown just inverse

 

[pbs681]

I've seen it
but it says sa sb are better when large
really?
my presim shown just inverse

What does it mean by "better" here is that, bigger sa and sb will have lesser stress effect. This is different issuea nd story.

For ur issue, u have to makesure that sa and sb in schematic and layout match!