isaacnewton
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Hello Everyone,
I have a question about Cadence post layout simulation. Please see the attached Figures.
Figure 1 is the Inverter schematic and symbol.
Figure 2 is the Testbench.
Figure 3 is the Schematic simulation waveform.
Fiugre 4 is the Inverter layout.
Figure 5 is the post layout simulation waveform.
From the Figures, you can see the the schematic simulation is perfect. But there are something wrong with the post layout simulation. It looks like the VDD and GND in the layout dose not connected the DC source and ground in the testbench.
In the layout, the symbolic pins were used.
gnd, vdd: inputOutput
A: input
Y: output
The layout passed DRC and LVS.
Anybody know the reasons? Does anybody meet the same problem?
Thank you in advance.
I have a question about Cadence post layout simulation. Please see the attached Figures.
Figure 1 is the Inverter schematic and symbol.
Figure 2 is the Testbench.
Figure 3 is the Schematic simulation waveform.
Fiugre 4 is the Inverter layout.
Figure 5 is the post layout simulation waveform.
From the Figures, you can see the the schematic simulation is perfect. But there are something wrong with the post layout simulation. It looks like the VDD and GND in the layout dose not connected the DC source and ground in the testbench.
In the layout, the symbolic pins were used.
gnd, vdd: inputOutput
A: input
Y: output
The layout passed DRC and LVS.
Anybody know the reasons? Does anybody meet the same problem?
Thank you in advance.