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#### isaacnewton

##### Full Member level 2
Hello Everyone,

Figure 1 is the Inverter schematic and symbol.
Figure 2 is the Testbench.
Figure 3 is the Schematic simulation waveform.
Fiugre 4 is the Inverter layout.
Figure 5 is the post layout simulation waveform.

From the Figures, you can see the the schematic simulation is perfect. But there are something wrong with the post layout simulation. It looks like the VDD and GND in the layout dose not connected the DC source and ground in the testbench.

In the layout, the symbolic pins were used.
gnd, vdd: inputOutput
A: input
Y: output

The layout passed DRC and LVS.

Anybody know the reasons? Does anybody meet the same problem?

#### cetc1525

##### Full Member level 3
I think you should add pin to vdd &gnd.

#### Hughes

isaacnewton said:
It looks like the VDD and GND in the layout dose not connected the DC source and ground in the testbench.
I agree with you. So, how do you add the stimuli for the post-layout simulation? I found diva has some problem with global netname (names ends with an exclamation) in extracted view. You may set the netlist mode as hierarchy, then "create final" to find what names the 'vdd!' and 'gnd!' is translated into the spice netlist. Then use that names to add stimuli for power.

#### Johnson

Device W/L ration also must be checked!

#### isaacnewton

##### Full Member level 2
cetc1525 said:
I think you should add pin to vdd &gnd.

I tried to add two more pins for 'vdd' and 'gnd' in the Schematic and Symbol. It works. But I don't want to add two more pins, because the symbol doesn't look nice with two more pins, and it's not convenient.

#### isaacnewton

##### Full Member level 2
Johnson said:
Device W/L ration also must be checked!

The device W/L ratios are ok, because it passed DRC and LVS.

#### isaacnewton

##### Full Member level 2
Hughes said:
I agree with you. So, how do you add the stimuli for the post-layout simulation? I found diva has some problem with global netname (names ends with an exclamation) in extracted view. You may set the netlist mode as hierarchy, then "create final" to find what names the 'vdd!' and 'gnd!' is translated into the spice netlist. Then use that names to add stimuli for power.

I used the testbench in Figure 2 for both schematic simulation and the post-layout simulation.

#### Hughes

isaacnewton said:
I used the testbench in Figure 2 for both schematic simulation and the post-layout simulation.

Then this is because Analog Artist can not recognize global net names in extracted cell views. Some one has raised this question in this forum. I have run into such problem too -- Sometimes Analog Artist treats 'vdd!' in extracted view as global net; sometimes as a local net name. My solution is:
(1) Add another pair of pins -- vdd and gnd to the layout and symbol. This was discussed above.
(2) Use textual stimuli. Take hspiceS for example. Create a stimuli file (ascii format) with the following lines:
Code:
vdd vdd! 0 2.5
vss gnd! 0 0.0
va A 0 pulse 0.0 2.5 0.0 500p 500p 10n 20n
Select the extracted view (not the testbench schematic) as the design to simulate, and choose the above-mentioned textual stimuli by fill in the field 'Stimulus File' field in the 'Environment Options' form with the path of stimulus file.
The names vdd! and gnd! should be checked with the Final Netlist.

#### isaacnewton

##### Full Member level 2
Hughes said:
Then this is because Analog Artist can not recognize global net names in extracted cell views. Some one has raised this question in this forum. I have run into such problem too -- Sometimes Analog Artist treats 'vdd!' in extracted view as global net; sometimes as a local net name.
Is it a bug of Cadence Analog Artist?

#### Hughes

Maybe, but I am not quite sure.

#### isaacnewton

##### Full Member level 2
Hughes said:
Then this is because Analog Artist can not recognize global net names in extracted cell views. Some one has raised this question in this forum. I have run into such problem too -- Sometimes Analog Artist treats 'vdd!' in extracted view as global net; sometimes as a local net name. My solution is:
(1) Add another pair of pins -- vdd and gnd to the layout and symbol. This was discussed above.
(2) Use textual stimuli. Take hspiceS for example. Create a stimuli file (ascii format) with the following lines:
Code:
vdd vdd! 0 2.5
vss gnd! 0 0.0
va A 0 pulse 0.0 2.5 0.0 500p 500p 10n 20n

Thank you very much for your clear explaination. I tried the stimuli method, it works.

If I want to put a load capacitor (200fF) at the output, can I add another line to the stimuli text file? Like
Code:
CL Y 0 200f
I tried to add the above line to the simuli file, it looks like it doesn't make any difference.

#### Hughes

isaacnewton said:
If I want to put a load capacitor (200fF) at the output, can I add another line to the stimuli text file? Like
Code:
CL Y 0 200f
I tried to add the above line to the simuli file, it looks like it doesn't make any difference.

You are right. Add the code above will put a load capacitor at the output. If it doesn't work, you may first check the final netlist and make sure the output node is netlisted as 'Y'. If so, you may increase the CL to a abnormally large value, say, 200n. This will give a quite different result even if the inverter have a large drive capability.

Note that you should explicitly re-netlist after you change your stimulus file. Otherwise, Analog Artist will not see the change in stimulus file and use the original netlist to simulate.

#### isaacnewton

##### Full Member level 2
Hughes said:
Note that you should explicitly re-netlist after you change your stimulus file. Otherwise, Analog Artist will not see the change in stimulus file and use the original netlist to simulate.
What do you mean by "explicitly re-netlist"? Thanks.

#### Hughes

I mean you should choose 'Simulate / Netlist / Create Raw' and 'Simulate / Netlist / Create Final' to re-netlist the design. The former step (Create Raw) may be bypassed -- but I am not sure -- you may have a try.

#### isaacnewton

##### Full Member level 2
Hughes said:
I mean you should choose 'Simulate / Netlist / Create Raw' and 'Simulate / Netlist / Create Final' to re-netlist the design. The former step (Create Raw) may be bypassed -- but I am not sure -- you may have a try.

Thx, Hughes. The 'Create Raw' can not be bypassed.

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