a question about bandgap circuit

[xz781122]

I want to design a CMOS bandgap circuit.So I have to use PMOS to form the diode(the diode 3 in the figure).But how can i simulate this diode?Can i use only source node and bulk node to form a diode(just as in figure) and put this diode in my circuit directly?I have done a simulation of this diode in hspice.but i can't get the correct V-I curve.How shall i do to form a diode with CMOS process.

 

[aryajur]

For implementing the diode in the bandgap you have to use a Lateral BJT that forms in the CMOS process, as shown in the figure. In this PNP BJT your collector is the substrate and that is grounded if you ground the base (N-well) and then use the source/drain of the transistor you can use it as a diode for Bangap circuits.
But this shows the layout picture. To use it for simulation you have to get the Lateral BJT models of the CMOS technology you are working with. You should be able to get them from whoever is supplying you the normal MOS transistor models.
Use that BJT model which they give and connect the BJT as a diode as described above(Grounding Base and Collector and using Emitter as diode p junction) And use it in your bandgap circuit.
That is how it should be done.

 

[sunking]

why not use vertal pnp? it is very popular in designing cmos banggap.

 

[huojinsi]

To aryajur
Why doesn't it use parasitic vertical PNP transistor as a diode in CMOS bandgap reference circuit?

 

[Robert Qi]

Generally, foundry will offer you with bjt gds and spice model. U can use them directly. It is no need to design the bjt youself, or you cannot get the spice model parameters of your bjt.

 

[aryajur]

I am sorry for the wrong wordings. I meant the vertical BJT.

 

[vonleo]

if lateral BJT is available, I guess it is more efficient than vertical one.

 

[rfsystem]

The lateral Poly-PNP (PPNP or LPPNP) bjt is called poly because the base width is defined by the gate poly channel length. It is in effect an 5-terminal device.

P: Gatepoly
B: Base NWELL
E: Inner P+ Region
C: Outer P+ Ring

The current gain is w/o an N* buried layer between 2-10. That is enough to use the PPNP as an amplifier. The collector current is converted into resistors with give about 10-20 as voltage gain. That reduces the offset requirement by orders of magnitude in terms of area for the error amplifier. That is typical a PMOS.

The problem is that foundries rarely model this device. There are huge number of devices which you can use to improve your designs. But foundries are gate processors.

 

[jcpu]

Dear Sir:

How would you use such a PPNP device?
There is no such thing in most of circuit simulators.

Practically, we might have to tight the poly gate to AVDD?
For modeling or simulation purpose.

 

[rfsystem]

I suggest to use an emitter ratio as in a classical PTAT cell. The number of parallel connected emitters are in series with the PTAT current defining resistor. The collector current difference is amplified by two poly resistors or NMOS in linear mode. The voltage difference is further amplified by a PMOS stage with folded cascode. The amplifier drives then the bandgap voltage direct. The base of the PPNP is connected to VSS. The bias voltage drop across the poly resistor should be less than 10-15*VT.

The model of the PPNP is a subcircuit with 2-3 PNPs and the PMOS. The poly is regular connected to the emitter. That gives some channel inversion and reduce the flicker noise.