A question about AMS high voltage cmos layout

[sear]

hv cmos layout

I am drawing layout with AMS 50V high voltage CMOS process and I am using calibre from verification. I found one problem when I do DRC check.

I draw two inverters by connection the output of the first one to the input of the second one. I used nmos20hs and pmos20hs devices. I always got DRC errors saying that the gate of the second inverter is floating. Actually it is connected to the output of the first inverter. I tried LVS, the layout and the schematic matches.

I also tried to implemented the inverters with other devices like nmos20h and pmos20h. The DRC errors disappeared. It seems that calibre does not consider nmos20hs and pmos20hs as transistors and it got wrong results.

Anyone have ever used these symmetrical devices? How could we remove these DRC errors?

Thanks a lot.

 

[hqqh]

bugs in calibre in layout

Hi,

it seams to be a bug in the calibre-drc rule file of the AMS hit-kit. Which version of hit-kit, do you have installed? Maybe an update can solve the problem? Do you have the possibility to use assura drc to test, whether it is an bug in calibre?

Regards
hqqh

 

[sear]

problems faced during drawing cmos layout

Hi,

Thanks for the reply. My hit-kit version is 3.72. I can not try with assura because the version of assura is too low.

regards

 

[hqqh]

high voltage cmos

Hi Sear,

if I have time next week, I will try the same drc with assura. You simply draw a schematic with two inverters using these 20V devices and then did the layout synthesis using Virtuoso XL. Is this the case?

Regards
hqqh

 

[sear]

high voltage cmos design with ams

Thank you so much for your help. Yes, the circuit is a simple inverter chain. The error only appears when I use symmetrical devices pmos20hs and nmos20hs in the first inverter.

Thanks.

 

[tandy]

would you please upload the layout of the inverter. and I am working on the same case.