a problem that simulate using modelsim simulator

[floatgrass]

verlog simulation using modelsim,there is a error:

Error: F:/myftp/mlf/mlf code/MLF 0116(end)/generic_dpram.v(887): $hold( posedge CLKB &&& re_flagB:1600 ns, WENB:1600 ns, 1 ns );


please tell me how to solve it.
thanks

 

[dada1019]

I think it implies that there are some hold time violation in your design which happen between the clk and re_flag signal.

 

[floatgrass]

the problem is that this error happen at funtional simulation using artisan ram verilog model.

 

[fpga123]

so, if you want to avoid this error inf, you could shut down the specify statement in ram module!

 

[ic_design]

You can ignore it.