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a problem about configuration for xilinx FPGA using a CPLD

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Newbie level 4
Feb 13, 2003
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Toronto, Canada
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I use a CPLD (XC9572) and an FLASH ROM to config the FPGA XC2S50 and the configuration mode is slave parallel.For the first time I succeede,the FPGA works well.But for the seconde time,the FPGA is damaged.
I have some questions as follows:
1. Is it necessary that PROG pin going high before INIT pin going high?
2. When loading configuration data to the FPGA,if the density of my FLASH ROM is larger than the need of the FPGA's configuration,how can I know the configuration is finished? If the configuration is finished indeed,but CPLD still loads the data into the FPGA,what will happen?Can FPGA be damaged?

Can anybody help me?Thank u.
My english is not good,because my mother tongue is not english.

Hi deebar,

I don't think is that easy to fry an FPGA.

You have to drive PROG# low for a period longer than XX (check the datasheet), imaging 300ns.

Then DONE and INIT# go low.

The INIT# stays low for some time (in this time the FPGA is clearing the internal memory), when it finishes it goes high.

Then you start clocking data in until the DONE signal goes high, that means you have finished and don't need to push any more data in.

If you are clocking data in an INIT# goes low bad news, it implies CRC Error.

There are two very common mistakes.

-byte swapping

flash_data(0) -> D7 in FPGA
flash_data(7) -> D0 in FPGA

This depends of the format you are using in your file, for RBT and BIT files the data must be byte swapped (if is not dine in HW). The HEX format can be swapped or not, depends of a flga in the generation of your file (for exmaple PromGEN in ISE)

-The settings in the generation of your file are not right.
There are lots of settings there, for exmple if you protect your FPGA agains reporgramming you want be able to reprogram it twice.
Have a look to them

I hope it helps and good luck


It might be possible to burn the FPGA, if you pull the PROGRAM pin low for extended periods of time. I've never experienced any problems related to that, but the Xilinx data sheets mention the problem.

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