a new question about prime power

[uil]

high_fanout_net_threshold example

1,prime power get the netlist without have no clock tree,but more than 30%power come from the clock tree ,so the result is so small, how to get a more accurate result before we add the buffer in the clock network ?
2,in the prime power ,the command set_multi_vdd can set the cell voltage with more than 1 rail ,for example ,the padring include 1.8 v and 3.3v,but in the lib,we get the information of padring'supply voltage,should i set it with the command ?
thanks for your help !!!!

 

[reaper]

uil,

I may be able to help for question number 1 as I believe it parallels my own experience in Power Compiler. Let me first make sure I understand your question. I believe you are telling me that you have no clock trees in your design. It is post synthesis but no layout or clock tree insertion has occurred.

You have run some power analysis and despite the lack of clock trees, some clock related elements are consuming large amounts of power. Is that correct?

I believe the reason that this occurs is due to the visible loads to the driver of the clock tree. So, you may have a mux that it driving your clock tree. Eventually, the output of that mux may only drive a single buffer which then fans out to your entire clock tree. But in the meantime, that mux is connected to every single receiver element in the clock tree. This could be hundreds or thousands of gates.

So, Prime Power, is trying to calculate how much power that mux would require to drive that enormous load. Such a load does not exist in the .lib power table. So, it interpolates a power values based on the information it does have. In doing so, it interpolates an absolutely huge number.

I am currently running Power Compiler and am trying to address this issue in 2 ways. The first is to just discount high fanout net power since we don't really have clock trees. I am doing this by setting a parameter called high_fanout_net_threshold to 0. This basically detects a high fanout net and zeroes out the load. You should be able to read a more detailed explanation on solvenet. The benefit of this approach is it gives you a decent power analysis of the rest of the design and you can move forward on reducing power in those other areas if that is your goal. The downside is that it produces an unrealistically optimistic power number for the total power since clock netweorks are unaccounted for.

The other way I am planning to attack it is to try to use the balance_buffer command to insert a rudimentary clock tree into the design on these high fanout nets. I have been unsuccessful so far in pursuing this methodology.

Perhaps these methodologies are also available in Prime Power.

If anyone has some better suggestions or some advice on using balance_buffer for me, I'd me glad to hear it.

Hope that helpes

thanks, reaper