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A DFT Problem in Mbist -----Low faults coverage in Mbist!

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bendrift

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mbist

in my design ,i wrap all the ram with mbist.
after i insert dft and run atpg, i find the mbist decrease the faults coverage of the design.
here,i paste the report of tetramax and the mbist code for discuss :)

#faults testcov instance name (type)
------- ------- -----------------------
51340 74.40% /vitcore/acs_datapath/acsram_fsm (vit_acsram_fsm_test_1)
10356 100.00% /vitcore/acs_datapath/acsram_fsm/btfram_ctl (vit_btfram_ctl_test_1)
10240 67.96% /vitcore/acs_datapath/acsram_fsm/ram_2 (vit_acsram_0_test_1)
5110 67.90% /vitcore/acs_datapath/acsram_fsm/ram_2/LRAM (dpreg16x80_0_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_2/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_0_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_2/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5110 67.90% /vitcore/acs_datapath/acsram_fsm/ram_2/URAM (dpreg16x80_1_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_2/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_1_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_2/URAM/dpreg16x80_inner (dpreg16x80_inner)
10236 67.94% /vitcore/acs_datapath/acsram_fsm/ram_4 (vit_acsram_1_test_1)
5106 67.87% /vitcore/acs_datapath/acsram_fsm/ram_4/LRAM (dpreg16x80_2_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_4/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_2_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_4/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5110 67.89% /vitcore/acs_datapath/acsram_fsm/ram_4/URAM (dpreg16x80_3_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_4/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_3_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_4/URAM/dpreg16x80_inner (dpreg16x80_inner)
10240 67.97% /vitcore/acs_datapath/acsram_fsm/ram_3 (vit_acsram_2_test_1)
5114 67.94% /vitcore/acs_datapath/acsram_fsm/ram_3/LRAM (dpreg16x80_4_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_3/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_4_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_3/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5106 67.87% /vitcore/acs_datapath/acsram_fsm/ram_3/URAM (dpreg16x80_5_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_3/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_5_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_3/URAM/dpreg16x80_inner (dpreg16x80_inner)
10240 67.96% /vitcore/acs_datapath/acsram_fsm/ram_1 (vit_acsram_3_test_1)
5110 67.89% /vitcore/acs_datapath/acsram_fsm/ram_1/LRAM (dpreg16x80_6_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_1/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_6_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_1/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5110 67.90% /vitcore/acs_datapath/acsram_fsm/ram_1/URAM (dpreg16x80_7_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_1/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_7_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_1/URAM/dpreg16x80_inner (dpreg16x80_inner)

[
 

dft problem

There are many mbist algorithms, each covers different faults. You may try to implement more algorithms in your mmemory wrapper.

Such as, march 14N and checkboard, etc. Of course, you also have to consider
the cost and resources to implement them.
 

mbist algorithms

I just mean that Mbist wrap decrease the whole design stuck at faults coverage not the memory test.
for the Mbist wrap have compare logic ,and compare logic was bounded at "111111" or '000000" ,so after insert dft ,atpg can not detected the stuct at faults of the compare logic. how can i do now ?
 

dft ram

hello, perhaps you should use bypass signal bypass your ram micro in atpg test

mode.





bendrift said:
in my design ,i wrap all the ram with mbist.
after i insert dft and run atpg, i find the mbist decrease the faults coverage of the design.
here,i paste the report of tetramax and the mbist code for discuss :)

#faults testcov instance name (type)
------- ------- -----------------------
51340 74.40% /vitcore/acs_datapath/acsram_fsm (vit_acsram_fsm_test_1)
10356 100.00% /vitcore/acs_datapath/acsram_fsm/btfram_ctl (vit_btfram_ctl_test_1)
10240 67.96% /vitcore/acs_datapath/acsram_fsm/ram_2 (vit_acsram_0_test_1)
5110 67.90% /vitcore/acs_datapath/acsram_fsm/ram_2/LRAM (dpreg16x80_0_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_2/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_0_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_2/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5110 67.90% /vitcore/acs_datapath/acsram_fsm/ram_2/URAM (dpreg16x80_1_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_2/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_1_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_2/URAM/dpreg16x80_inner (dpreg16x80_inner)
10236 67.94% /vitcore/acs_datapath/acsram_fsm/ram_4 (vit_acsram_1_test_1)
5106 67.87% /vitcore/acs_datapath/acsram_fsm/ram_4/LRAM (dpreg16x80_2_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_4/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_2_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_4/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5110 67.89% /vitcore/acs_datapath/acsram_fsm/ram_4/URAM (dpreg16x80_3_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_4/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_3_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_4/URAM/dpreg16x80_inner (dpreg16x80_inner)
10240 67.97% /vitcore/acs_datapath/acsram_fsm/ram_3 (vit_acsram_2_test_1)
5114 67.94% /vitcore/acs_datapath/acsram_fsm/ram_3/LRAM (dpreg16x80_4_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_3/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_4_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_3/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5106 67.87% /vitcore/acs_datapath/acsram_fsm/ram_3/URAM (dpreg16x80_5_test_1)
2966 71.69% /vitcore/acs_datapath/acsram_fsm/ram_3/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_5_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_3/URAM/dpreg16x80_inner (dpreg16x80_inner)
10240 67.96% /vitcore/acs_datapath/acsram_fsm/ram_1 (vit_acsram_3_test_1)
5110 67.89% /vitcore/acs_datapath/acsram_fsm/ram_1/LRAM (dpreg16x80_6_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_1/LRAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_6_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_1/LRAM/dpreg16x80_inner (dpreg16x80_inner)
5110 67.90% /vitcore/acs_datapath/acsram_fsm/ram_1/URAM (dpreg16x80_7_test_1)
2970 71.73% /vitcore/acs_datapath/acsram_fsm/ram_1/URAM/U_bt_sram (bt_reg_WE_WIDTH1_ADDR_WIDTH4_DATA_WIDTH80_7_test_1)
348 0.00% /vitcore/acs_datapath/acsram_fsm/ram_1/URAM/dpreg16x80_inner (dpreg16x80_inner)

[
Click to expand...
 

dft faults

i have by pass the signal before ram,but the mbist tie some signal at "000000' or "111111" for bist compare,it decrease the fault coverage!
 

Generally we don't test the Bcon and please add no fault to them.
 

Re: mbist algorithms

Yes, bound some point will decrease the converage.
 

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