Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

A confused problem about Clock Tree Synthesis!?

Status
Not open for further replies.

Archers

Newbie level 4
Joined
Apr 18, 2011
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Beijing,China
Activity points
1,309
Hi,friends,
I have a problem about CTS(clock tree synthesis).Now I need to do the CTS by Perl script,there have uncertain buffer array,the row of the buffer array is 3,but the column of
the array is not sure,we can use the "N" stand for the column.Next I have to do is generate the clock tree,you know,we must ensure the clock from input to output have the same delay,in other words,Clock through the same series of the buffers,all the things have to be done by perl script,but I have no idea,who can help me,if you give me some idea,I will appreciate with you.
Thank you in advance!
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top