A challenge: I need to disable reset after reset.

[userx2]

Hello folks

I have to try and correct someone else's poor design here on a something.

This has a Lattice M4A5 PLD.

This design is basically a address decoder and it also contains 2 enable lathes. It has no clock.
It has a read and a write line going into it and a reset line driven from an RC reset circuit.

The 2 latches get set once a write to a certain address occurs. They can not be reset unless an external reset occurs.
They are used to keep an external circuit disabled until the host cpu has booted up and enables the latches.

The problem is that external factors cause spikes on the reset input of this design and this in turn resets the internal latches, disabling vital external circuitry.

So I had the brilliant idea that I can disbale the reset (internally in the PLD) after it has occured once after power up.

So far, I have not been able to come up with a solution since I cannot think of anything I can use a deciding factor to disable the reset.

The code is written in AbelHDL.

Perhaps someone else has an opinion on how this can be done or if it can even be done within the constraints of no clock etc.

Best regards
X

 

[ads_ee]

Hello folks

I have to try and correct someone else's poor design here on a something.

The problem is that external factors cause spikes on the reset input of this design and this in turn resets the internal latches, disabling vital external circuitry.

X

WTF!?

Let me guess the reset is not an active low reset and you're getting cross talk on the reset line causing runt pulses to show up on the reset line.

Can you add another latch for disabling the reset like the two enable latches? This will only work if the reset isn't some hardwired rest that goes to all the storage elements in the PLD.

 

[userx2]

WTF!?

Let me guess the reset is not an active low reset and you're getting cross talk on the reset line causing runt pulses to show up on the reset line.

Can you add another latch for disabling the reset like the two enable latches? This will only work if the reset isn't some hardwired rest that goes to all the storage elements in the PLD.

You are correct!
Someone designed the reset as active high and used an RC netword to do it. It gets high frequency crosstalk from the Vcc line. It is easy to fix in hardware but because there are so many of these, it would be best if there were a 'soft' solution.

I have already thought about extra latches that will disable the reset but I seem to go in circles in that any such latch can come up in the wrong state at power up and thus disabling reset already.
Unless there is a way to get a latch to initialise in a given state without reset, then I am out of ideas.


Regards
X

 

[ads_ee]

Unless I'm mistaken the part you are using is an ispMACH 4A device?

According to the documentation on page 22 of **broken link removed**



You should be able to force a low (reset) on the register that generates the reset_disable control.

 

[userx2]

Unless I'm mistaken the part you are using is an ispMACH 4A device?

According to the documentation on page 22 of **broken link removed**

View attachment 86080

You should be able to force a low (reset) on the register that generates the reset_disable control.

Hello

Thank you very much for that info.
If that works, then there is no need for an external reset at all in this case and I may be able to just not use that reset input at all !

I have no idea though how I canconfigure the macrocell flip-flops to do that.
The AblelHDL reference manual does not offhand seem to mention any power up initialization.

Best regards
X

 

[ads_ee]

Can't you use Verilog or VHDL instead of AbelHDL?

Based on that ispMACH 4A datasheet if you code a reset it will use the reset/set equation to determine the power up value. If you don't code in a reset for the register it will power up 0.

 

[userx2]

Can't you use Verilog or VHDL instead of AbelHDL?

Based on that ispMACH 4A datasheet if you code a reset it will use the reset/set equation to determine the power up value. If you don't code in a reset for the register it will power up 0.

Hi
I don't think so. Their Lattice Diamond toolchain - which supports the Verilog / VHDL dowes not support these older chips :-(


I will do a few experiments and see what it does.
I will code a D-type Flip Flop (istype reg_d) , connect the .clk and.d signals to 0 and use the
asyncronous preset (.ap)to set it when required.
I will leave the reset (.ar) unconnected.

Let's see what it does.

Regards
X