ethan
Member level 3
Hello Everybody,
I attach a figure below which shows fully-differential fold-cascode one stage opamp with SC-CMFB. Then in my next post, there is another figure, which I think it can be used as CMFB structure with equavilent resistors (which I call R-CMFB here).
This CMFB structure is variant from Razavi book on page 442 (chapter 12), or in lecture 21 of
**broken link removed**
the circuit description is in this lecture "Passive CMFB(1)"
Instead of connecting feedback control point to tail current source of the input stage, I connected it to the top PMOS current source of the cascode stage.
The switches I used in clock phase 2 are transmission gate with min. in length and double min width for PMOS, NMOS with all min in width and length.
The switches I used in clock phase 1 are PMOS only, with min in length and double min width.
Clock frequency is 200kHz.
And I have tried the capacitor value between 100fF to 1pF (each) with almost same simulation results only in SC-CMFB structure; in R-CMFB, I only tried 500fF and 200kHz, whose equavilent resistor is 10M ohms each.
My questions are as following:
1. Do you agree that these two figures can be seen as equavilent in term of calculation and simulation purpose?
if no, would you please specify your ideal why they are not? Can you teach me
whether there is a way to get an equavilent R-CMFB structure?
2. if these are same in term of simulation purpose, currently, I can get open-loop DC gain with 70dB around with R-CMFB structure, and also get certain measure f-3b, unity gain frequency, phase margin for open-loop opamp.
However, I only can achieve 50dB open-loop DC gain for SC-CMFB by using PSS, PAC simulation, and much less unity-gain frequency comparing with previous case, and also very good PM (comparing previous).
I remember that someone mentioned in our forum before that for PAC, it calculates the whole period, so with half period SC structure, there is half energy loss, which in case you need to add 6 dB more on its PAC. I am wondering if this is always true in all the case, then how can we feel confidence with PAC simulation?
And also in Dr. Ken Kundert's paper about SC filters simualtion, he mentioned to add ideal S/H circuit and hence get expected result for PAC, except that there is coloring on your results.
So, even if I add 6dB more in my case, it is still not 70dB around.
I have even tried the SC-CMFB structure listed in that lecture 21 and Razavi book. same results with above, one is around 70dB (R-CMFB, open-loop), another is 48dB(SC-CMFB) in my design.
I know I must have done something wrong, but still couldn't figure it out for a while. But I am sure this time that I got proper clock timing diagram (sorry for before).
Can anybody instruct me on this confliction? Your suggestion is really appreciate.
3. This question is asking about between ideal S/H circuit and SC filter simualtion method.
I would like to know whether it is necessary for all cases with SC type circuits, to add an ideal S/H following the outputs in order to get the PAC output. Since, in some cases, if I only can get simulation results from PAC and ideal S/H always needed to deploy, then I thought I could not readout the accurate results from the plots, such as unit-gain frequency, because of sin(x)/x filtering.
Please correct me if I am wrong.
I attach a figure below which shows fully-differential fold-cascode one stage opamp with SC-CMFB. Then in my next post, there is another figure, which I think it can be used as CMFB structure with equavilent resistors (which I call R-CMFB here).
This CMFB structure is variant from Razavi book on page 442 (chapter 12), or in lecture 21 of
**broken link removed**
the circuit description is in this lecture "Passive CMFB(1)"
Instead of connecting feedback control point to tail current source of the input stage, I connected it to the top PMOS current source of the cascode stage.
The switches I used in clock phase 2 are transmission gate with min. in length and double min width for PMOS, NMOS with all min in width and length.
The switches I used in clock phase 1 are PMOS only, with min in length and double min width.
Clock frequency is 200kHz.
And I have tried the capacitor value between 100fF to 1pF (each) with almost same simulation results only in SC-CMFB structure; in R-CMFB, I only tried 500fF and 200kHz, whose equavilent resistor is 10M ohms each.
My questions are as following:
1. Do you agree that these two figures can be seen as equavilent in term of calculation and simulation purpose?
if no, would you please specify your ideal why they are not? Can you teach me
whether there is a way to get an equavilent R-CMFB structure?
2. if these are same in term of simulation purpose, currently, I can get open-loop DC gain with 70dB around with R-CMFB structure, and also get certain measure f-3b, unity gain frequency, phase margin for open-loop opamp.
However, I only can achieve 50dB open-loop DC gain for SC-CMFB by using PSS, PAC simulation, and much less unity-gain frequency comparing with previous case, and also very good PM (comparing previous).
I remember that someone mentioned in our forum before that for PAC, it calculates the whole period, so with half period SC structure, there is half energy loss, which in case you need to add 6 dB more on its PAC. I am wondering if this is always true in all the case, then how can we feel confidence with PAC simulation?
And also in Dr. Ken Kundert's paper about SC filters simualtion, he mentioned to add ideal S/H circuit and hence get expected result for PAC, except that there is coloring on your results.
So, even if I add 6dB more in my case, it is still not 70dB around.
I have even tried the SC-CMFB structure listed in that lecture 21 and Razavi book. same results with above, one is around 70dB (R-CMFB, open-loop), another is 48dB(SC-CMFB) in my design.
I know I must have done something wrong, but still couldn't figure it out for a while. But I am sure this time that I got proper clock timing diagram (sorry for before).
Can anybody instruct me on this confliction? Your suggestion is really appreciate.
3. This question is asking about between ideal S/H circuit and SC filter simualtion method.
I would like to know whether it is necessary for all cases with SC type circuits, to add an ideal S/H following the outputs in order to get the PAC output. Since, in some cases, if I only can get simulation results from PAC and ideal S/H always needed to deploy, then I thought I could not readout the accurate results from the plots, such as unit-gain frequency, because of sin(x)/x filtering.
Please correct me if I am wrong.
