A better way to write a Demux ?

[Nikolai]

The following is the code im using to write a Demux. It is working fine.
But XST is issuing a warning :

Xst:737 - Found 8-bit latch for signal <O0>.
WARNING:Xst:737 - Found 8-bit latch for signal <O1>.
INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch.

So is there a better way to write a Demux ? I have also tried using "case" and concurrent "when" statements but i keep getting this warning.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Demux_64 is
Port ( Input : in STD_LOGIC_VECTOR (7 downto 0);
Select_line : in STD_LOGIC_VECTOR (2 downto 0);
O0 : out STD_LOGIC_VECTOR (7 downto 0);
O1 : out STD_LOGIC_VECTOR (7 downto 0);
O2 : out STD_LOGIC_VECTOR (7 downto 0);
O3 : out STD_LOGIC_VECTOR (7 downto 0);
O4 : out STD_LOGIC_VECTOR (7 downto 0);
O5 : out STD_LOGIC_VECTOR (7 downto 0);
O6 : out STD_LOGIC_VECTOR (7 downto 0);
O7 : out STD_LOGIC_VECTOR (7 downto 0));
end Demux_64;

architecture Behavioral of Demux_64 is

begin

process (Input,Select_line)

begin

if (Select_line = "000") then
O0 <= Input;
elsif (Select_line = "001") then
O1 <= Input;
elsif (Select_line = "010") then
O2 <= Input;
elsif (Select_line = "011") then
O3 <= Input;
elsif (Select_line = "100") then
O4 <= Input;
elsif (Select_line = "101") then
O5 <= Input;
elsif (Select_line = "110") then
O6 <= Input;
else O7 <= Input;

end if;
end process;

end Behavioral;

 

[shawndaking]

well, cases are great i don't like the if statements - it seems that they are acting as latches, and ofcourse they prorities the inputs.

 

[Nikolai]

Yes latches are being inferred. Same is the case when is use "case" statements.
Functionally the code is correct. But the latches do seem out of place.

 

[Iouri]

use this code


O1 <= Input when select_line = "001" else (others => 'Z');


.....



O7 <= Input when select_line = "111" else (others => 'Z');

 

[xtcx]

Always prefer Case to If....I have felt the disadvantageous of using If-else based selection since after coding over some 2000 lines of code....More comaparision, to my point takes much synthesis time and maybe some gate resources. Should you need, use If state cautiously..

 

[kvingle]

use this code


O1 <= Input when select_line = "001" else (others => 'Z');


.....



O7 <= Input when select_line = "111" else (others => 'Z');

If you like to have tristate buffers inside the chip.....(very bad idea)

 

[Nikolai]

I want my Demux outputs to remain stable even after the select inputs change. So i cannot use tristates.

Basically i want to give a 8 bit input to eight 8 bit output lines one after the other while keeping output lines stable when select changes.

I guess latches is the only way to do it.

 

[kvingle]

ok....wait..

 

[Nikolai]

Thats the code for a mux ...
I need one for a Demux.