a basic question about the pll

[calven303]

hi!
i am a freshman in pll.i am reading best's book.i wonder if my understanding is right.
the book builds a linear model assuming the pll is in the locked state and the reference frequency is equal to the frequency of the divider's output signal(PD is a multiplier).but when the model is actually used,the reference frequency is not the same with the frequency of the divider's output signal(such as the referency frequency increases to another) while the pll is still in the locked model.why the model is still valid?we consider that the reference frequency does not change ,but the reference phase changes like a ramp function?
give me some advice,please
thanks a lot

 

[khouly]

the linear model if build for lock or near lock state , to give a simple formulas , abut how the PLL will act , but sure for the unlock or far from lock u need to model the PLL not in S domain ,
this also will show how the PLL will act , in the beginning of acquisition phase


khouly

 

[calven303]

i find i do not understand the concepts clearly!my questions are as follows:
1.the pll is in the unlocked state when either the frequencies or the phases are different?
2.the linear model is strictly valid only when both frequencies and phases are equal?
3.but we can consider the circuits is approximately linear and use the transfer function to get some approximate results if the change of the frequency is small(so the phase change is small)?
4.if the frequency change is small,the circuit change quickly from the nonlinear state to the approxiately linear state when we can use the transfer function?
5.we can use the transfer function to get the setting time ,but we have to use the nonlinear model to get the acqusition time?
thanks a lot

 

[khouly]

1) the PLL unclock when the error signal output form the phase detector is zero , coz some PDs output is zero when the phase difference is 90 degree , and the frequency' should be the same

2) the linear model is valid if the it is locked or near lock , this mean the phase and frequency difference is small

3) the lock time time can be get using the linear model but it is approxmation , u can get it more accuratly with the nonlinear

4) the acquisition time should be used with nonlinear model

khouly

 

[biff44]

Its not!

When the frequency of the divided down VCO is not yet equal to the frequency of the reference input to the phase detector, then the PLL is operating in a NON-LINEAR mode. The original linear model does not apply!

ONLY when the frequencies are close enough that the phase detector is operating within its 2Π to - 2Π region will the linear model apply again. The digital frequency discriminator in PLL chips is not linear at all.

you can find papers on the non-linear analysis of PLLs, especially for acquisition time estimates, online.

The ONLY way you can do a linear analysis if if you use a double loop. Such as if you sum the digital phase detector with an analog frequency discriminator.

 

[calven303]

thanks a lot
the frequcencies are close enough,but then are still different,right?then why the linear model is valid again when phase difference in the range of 2Π to -2Π?the linear range is so large?

 

[biff44]

Because the vout of the phase detector is directly proportional to the phase difference of the two inputs, it is monotonic, and for a digital phase detector it is fairly linear (ie follows a x mv/degree constant).

 

[calven303]

thanks a lot
but if the PD is a multiplier,will the linear range be much smaller because the real function is sin rather than linear?