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a basic doubt friends

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srinpraveen

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Hi friends i wrote a piece of verilog code for the following problem statement. (The paper is attached with this thread)

Read the SVM implementation paper (Omar Pina-Ramirez, Raquel Valdes-Cristerna, Oscar Yanez-
Suarez, “An FPGA Implementation of Linear Kernel Support Vector Machines,” in Proceedings of
the IEEE International Conference on Reconfigurable Computing and FPGA’s, pp.1-6, Sept. 2006).
Support Vector machine is a common learning technique for binary classification task. The standard
SVM takes a set of input data with known labels/classes (-1,1) as input and generate a general mathe-
matical model. For each new input, this model can predict which of two possible classes the input is
a member of. The model generation is called training which leads to Equation 1.
In this problem it is assumed that the training part is done and model is ready as expressed in
Equation 5. In this equation X is a vector of length 3 that defines the new input to be classified. Xi is
also a vector of length 3 that belongs to training set. yi is the corresponding class value of Xi which
could be -1 or 1. ai is an scalar value that is extracted from training phase and it has a different value
for each iteration. N is the number of iterations and it is equal to 4 for this problem. Consider
X, Xi, yi and αi to be inputs to the hardware and implement the SVM equation as it is explained in
Section 2.2. Assume all signals in datapath are 8-bit signed integer. For uniformity, assume we have
one 8-bit port for each of X, Xi, yi and αi (e.g. the unit reads three 8-bit numbers for vector X one
by one).
In this problem, you mainly implement a unit that computes Equation 5. The corresponding
flowchart is shown in Figure 1 with explanation of steps Section 2.2. Briefly, the first step is mul-
tiplication of two vectors that generate scalar value P. Second step is multiplication of an integer
value by 1 or -1 which is a sign change if it is -1. D is the scalar product of P and S. The accumulator
does the summation for 4 times (the value of A is zero at reset). The final step (1-bit output of your
design), decision making part, implements the “sgn” which is an inequality checking.
In your implementation, try to use a mix of behavioral and structural descriptions (as opposed to
pure behavioral). Slight modifications of design, compared to those provided in the paper, are allowed.



My code:
module regexp(clk, rst, X, Xi, yi, alphai, dw);
input clk;
input rst;
input [7:0]X;
input [7:0]Xi;
input [7:0]yi;
input [7:0]alphai;
output reg [7:0]dw;

reg [7:0]J[2:0]; //{ ............... , ..................., ...............}
reg [7:0]K[2:0];
reg [3:0]count=0;

reg signed [15:0]S;
reg signed [15:0]P;
reg signed [33:0]A;



reg signed [31:0]D;
reg signed [7:0]E;
reg signed [7:0]F;



parameter N=3'b100;


always @(posedge clk)
begin
E <= alphai;
F <= yi;
if(rst==1'b0)
begin

P<=0;
D<=0;
A<=0;


J[0]<=1'b0;
J[1]<=1'b0;
J[2]<=1'b0;

K[0]<=1'b0;
K[1]<=1'b0;
K[2]<=1'b0;

end

else
begin
//A<=0;
count <= count + 1;
J[0]<=X;
J[1]<=J[0];
J[2]<=J[1];

K[0]<=Xi;
K[1]<=K[0];
K[2]<=K[1];

P <= J[0]*K[0] + J[1]*K[1] + J[2]*K[2];

S <= E * F;


D <= P * S;
//if(count%3==3'b000)
A<= A + D;
//else
//A<= A;

end
end


always @(A)
begin
if(A>1'b0)
dw<=00000001;

else if(A==1'b0)
dw<=00000000;

else
dw<=11111111;
end
endmodule

Everything in this code which I wrote works perfectly in simulation in modelsim except for the output bit 'dw'. It was never going to 1 as was required in the question. If anyone could go through the code and spot any logical mistake, I would greatly appreciate it. I tried my best to sort out this issue myself (eg I changed some variables to signed and that removed most of the problems but the dw output just doesn't go to 1 when required)

Kindly help me out.
 

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N vijay kumar

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hi......
i am new to this..........

can we compare those two as they are different in port sizes.....?

as A(34 bit) and 1'b0(1 bit).........
 

srinpraveen

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Hi buddy..yes it can be compared..It wouldn't throw an error..
 

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