VHDL code for a 16*16 bit static RAM

[zilak]

Hello... I need the VHDL code for a 16*16 bit static RAM that works with/without read buffer and with/without partitioning...

Thank you in advance,
Zilak

 

[banjo]

vhdl ram

This is usually handled using specific tools from the FPGA vendor. The reason is it is implementation specific when most compact and efficient. If you are using Xilinx FPGAs, use the CoreGen tool to generate a VHDL module that will do this function. If you are using another vendor, search their toolset for something similar or visit their website.

 

[my_garden]

ram vhdl

Hi Zilak,
FYI.
-------------Pseudo Dual Port VHDL Example
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity daul_port_ram is
generic (data_width : natural := 8;
addr_width : natural := 16);
port ( clk_in : in std_logic;
clk_out : in std_logic;
we : in std_logic;
addr_in : in std_logic_vector( addr_width - 1 downto 0);
addr_out : in std_logic_vector( addr_width - 1 downto 0);
data_in : in std_logic_vector( data_width - 1 downto 0);
data_out : out std_logic_vector( data_width - 1 downto 0)
);
end daul_port_ram;

architecture daul_port_ram_arch of daul_port_ram is

type mem_type is array (2** addr_width downto 0) of std_logic_vector( data_width - 1 downto 0) ;
signal mem : mem_type ;

begin

mem_write : process (clk_in)
begin
if clk_in'event and clk_in = '1' then
if (we = '1') then
mem( conv_integer( addr_in)) <= data_in ;
end if ;
end if ;
end process write ;

mem_read : process (clk_out)
begin
if clk_out'event and clk_out = '1' then
data_out <= mem( conv_integer( addr_out)) ;
end if ;
end process read;

end daul_port_ram_arch;

 

[elec-eng]

ram vhdl code

attached is the vhdl and verilog codes of about 26 different types of rams

these codes are from xilinx XST userguide

they are :

 

[Mejdi_tn]

vhdl mem_type dual port

----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Titre : ram synthétisable
-- Projet :
-------------------------------------------------------------------------------
-- Fichier : ram_simple.vhd

-------------------------------------------------------------------------------
-- Description : RAM avec une seule adresse mais deux horloges
-- description conforme a la doc leo_tech.pdf page 292
-- surface occupee : 16 function generators

-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ram_simple IS
PORT (
SIGNAL data : IN std_logic_vector(7 DOWNTO 0);
SIGNAL address : IN std_logic_vector(4 DOWNTO 0);
SIGNAL we, inclock, outclock : IN std_logic;
SIGNAL q : OUT std_logic_vector(7 DOWNTO 0));


END ram_simple;


ARCHITECTURE fe2 OF ram_simple IS

TYPE mem_type IS ARRAY ( 31 DOWNTO 0) OF std_logic_vector (7 DOWNTO 0);
SIGNAL mem : mem_type;
SIGNAL address_int : unsigned(4 DOWNTO 0);

BEGIN -- ex2
l0 : PROCESS (inclock,outclock, we, address)

BEGIN -- PROCESS
IF (inclock = '1' AND inclock'event) THEN
address_int <= unsigned(address);
IF we = '1' THEN
mem(To_integer(unsigned(address))) <= data;
END IF;
END IF;
IF (outclock = '1' AND outclock'event) THEN
q <= mem(to_integer(address_int));
END IF;

END PROCESS;

END fe2;