I think you mean that 27MHz/9600 = 2812.5, so you can't use a simple counter to get an exact ratio.
If your 9600 output needs to have low jitter, you could double the 27 MHz clock by using a DLL or PLL or whatever feature your FPGA provides, and then divide the 54 MHz clock by 5625.
Another approach -- If you don't mind some jitter on the 9600 output, you could design a counter that divides the 27 MHz clock by 5625, and outputs two pulses during that time. The output's average frequency would be exactly 9600 Hz, but the output period would alternate between 2812 and 2813 cycles.