8051 - What happens when interrupt of same priority occur at the same time?

[mm_pk1]

What happens when the interrupts of same priority level occur at the same time? Let us say that Int0 and INT1 and 89C51 are set as high priority interrupt. Now what will happen if they occur at the same time. Would one of them will be ignored? or will both of them execute one after another? If later is the case, what will be serviced first?

Please help, i was unable to find the answer anywhere till now. Thanks

 

[sky_123]

I think it is impossible for two signals to arrive at the same time exactly (might defy a few physics rules).

 

[FvM]

Standard 89C51 doesn't have interrupt priority. For enhanced processors, that have this feature, e.g 89C51RD2, the question is answered in the data sheet.

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence.

As long as interrupt requests aren't reset intentionally, no interrupt event will be ignored.

P.S.:

I think it is impossible for two signals to arrive at the same time exactly.

Arrival within the same instruction cycle is sufficient.

 

[mm_pk1]

I think it is impossible for two signals to arrive at the same time exactly (might defy a few physics rules).

Both the signals can arrive at the INT0 and INT1 pins in the same clock cycle. One clock cycles of 1MHz crystal takes 1 micro seconds. So during this interval, it is definitly possible. Sorry, but my problem is still not resolved

 

[sky_123]

I think FvM has answered your question? All interrupts get serviced eventually, and an internal sequence gets used in the scenario that two interrupts occur within one clock cycle. If you really wanted to know which one arrived first (since they can't possibly arrive at the same time), then you need a higher clock speed.
By the way, it would seem odd to have a circuit where you needed to know which same-priority interrupt occurred first. In fact in many cases, people tie same-priority interrupts all to the same interrupt pin if they are (say) open collector - (i.e. you know an interrupt occurred, but you don't know which device caused it, so you read all the devices once you have determined that the interrupt occurred).
If you have same-pri interrupts and you really need to know which one occurred first and the possibility exists that it could occur within one clock cycle, then really you need some exernal circuit to the microcontroller to latch when a signal goes high first.

 

[FvM]

So during this interval, it is definitly possible.

Yes, I already mentioned that "simultaneous" arrival is possible.

Sorry, but my problem is still not resolved.

There is no problem at all. If you don't understand the short (but clear) datasheet quote in my previous post, you should read the applicable documentation of your processor.

 

[Kurenai_ryu]

also remember the phisical priority of the interrupts (which is the order in the interrupt table)

If two requests of different priority Ievels are received simultaneously, the request of
higher priority level is serviced. If requests of the same priority level are received
simultaneously, an internal polling sequence determine which request is serviced, Thus
within each priority level is a second priority structure determined by the polling
sequence, as follows:
Table 2-27. Interrupt Priority Level
Source Priority Within Level
1 IE0 (highest)
2 TF0
3 IE1
4 TF1
5 RI + TI
6 TF2 + EXF2 (lowest)

urg, sorry, it's just as FvM posted...