8051 OP code cycle time??

[nemolee]

instruction cycles 8051

Dear all,

As I know, the OP code cycle time of 8051 MCU is 4 cycles for maximum.
But today I heard from other people that the OP code cycle time is 12 cycles.
If you know, could you tell me why??
Thanks a lot.

Best regrads.

 

[XNOX_Rambo]

8051 1 cycle time

It depends on the brand. E.g. SiLabs have types that have 1 clock cycle OP:s
and that run at 100 MHz clock.

 

[wek]

The "traditional" 8051 has instruction cycles = 12 oscillator cycles. Each instruction can take one, two or four instruction cycles to complete. For example, LJMP takes 2 instruction cycles, it means 2*12=24 oscillator cycles, so using 12MHz crystal a LJMP takes 2us to execute.

Newer derivatives have less oscillator cycles per instruction cycle; and also the number of instruction cycle per instruction can be different from the traditional 8051.

http://www.efton.sk/t0t1/8051cs.pdf
http://www.efton.sk/t0t1/8051op.pdf
http://www.efton.sk/51comp/51comp.htm

and a zillion of other resources.

wek

 

[bobsanjose]

Wek did a great job explaining the difference between oscillator cycles and instruction cycles.
If you were thinking 4 cycles you might be using a Dallas device which works in the performance range.
The good old 51 needed 12 oscillator cycles for an instruction cycles, then there were many devices with a 6-clock option, timing compatible, everything was just twice as fast, the fastests timing compatible devices today are 2-clock devices, e.g. the LPC900 which are EXACTLY 6 times faster than a 12 clock executing the same instructions.
If you go to the "so called single clock" devices from Silabs or Atmel (the 51s), you will find that there are one cycle, two cycle, and multiple cycle instructions but the truth is, they are fast than two cycle devices. Not twoce as fast but faster. If anything in your system depends on timing cmpatibility, hands off from these devices, if it is about more performance, the so called single clock devices are faster than 2-clock devices but not twice as fast as the 1-clock would indicate.
For an original 51-architecture specification you can check this document:
**broken link removed**
it includes instruction cycles times based on the 12-clock implementation. External clock was 12 MHz and one instruction cycle time was 1usec.

More 51-originals can be found here:
**broken link removed**

hope this helps to understand the different "cycles" in the 51-world a little bit.

Bob

 

[XNOX_Rambo]

Wek and Bob have explained everything thoroughly, I'd just like to add a
general tip - no, a plead; read the datasheet of the actual chip you intend to
use and read all of it.
Every chip - even from the same vendor and family - should be regarded as
unique. The days of using generic LSTTL chips are long gone...