8-to-1 MUX (accessing vectors)

[Opel_Corsa]

8 to 1 mux

I am trying to write a code for an 8-to-1 mux. Here's what I've got so far:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mux8to1 is
	port (X: in  std_logic_vector(7 downto 0);
		  S: in  std_logic_vector(0 to 2);
		  F: out std_logic);
end mux8to1;

architecture RTL of mux8to1 is
begin
	process(X,S)
	begin
		if (S=0) then
			F <= X[0];
		elsif (S=1) then
			F <= X[1];
		elsif (S=2) then
			F <= X[2];
		elsif (S=3) then
			F <= X[3];
		elsif (S=4) then
			F <= X[4];
		elsif (S=5) then
			F <= X[5];
		elsif (S=6) then
			F <= X[6];
		elsif (S=7) then
			F <= X[7];
		end if;
	end process;
end RTL;

In the above, X is the 8-bit input, S is the 3-bit switch, and F is the single bit output. I think my question is how to access values within a vector? (in my case, X[0] doesn't seem to be in the correct format)
Also, I don't think something like S=1 is meaningful in VHDL (I use Quartus btw). Is there a way to use decimals instead of binary? i.e. to type S=1 instead of typing S="001"

Any help is appreciated.

 

[richardyue]

vhdl mux

I have the same problem when I program with VHDL.

 

[Opel_Corsa]

vhdl 8 to 1 mux

I think my question is how to access values within a vector? (in my case, X[0] doesn't seem to be in the correct format)

I just figured out I had to use ( ) instead of [ ] and it worked. But still need help with representing numbers in decimal instead of binary.

 

[nand_gates]

8 to 1 multiplexers

VHDL is strongly typed language. Means it will not do type conversion automatically.
You will have to take care of type conversion using functions like to_integer. here is
how you can write ur mux.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity mux8to1 is
   port (X: in  std_logic_vector(7 downto 0);
        S: in  std_logic_vector(2 downto 0);
        F: out std_logic);
end mux8to1;

architecture RTL of mux8to1 is
begin
  F <= X(to_integer(S));
end RTL;

 

[Opel_Corsa]

8to1mux

thanks for the help but my compiler couldn't recognize "to_integer". do i need an additional library? my compiler is quartus II

 

[issaiass]

vhdl program code for 8 to 1 mux

You need the tree standar libraries and the function

CONV_INTEGER()

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

this should be enough.

/////////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux8to1 is
port (X: in std_logic_vector(7 downto 0);
S: in std_logic_vector(2 downto 0);
F: out std_logic);
end mux8to1;

architecture RTL of mux8to1 is
begin
F <= X(CONV_INTEGER(S));
end RTL;

 

[nand_gates]

mux 8 input

Checkout this!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mux8to1 is
   port (X: in  std_logic_vector(7 downto 0);
        S: in  std_logic_vector(2 downto 0);
        F: out std_logic);
end mux8to1;

architecture RTL of mux8to1 is
begin
  with S select
    F <=
    X(0) when "000",
    X(1) when "001",
    X(2) when "010",
    X(3) when "011",
    X(4) when "100",
    X(5) when "101",
    X(6) when "110",
    X(7) when "111",
    'X'  when others;
end RTL;

 

[Opel_Corsa]

8-to-1 mux

great, thanks. working fine!