Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

8 point fft using ipcore

Status
Not open for further replies.

Sharmi703@gmail.com

Newbie level 1
Joined
Mar 25, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
20
Hi i have designed 8 point fft v7.1 using logicore 12.3... simulation is done.. but my output is full zero... the input which i m giving its taking....pls any1 help me..

My testbench code


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
module tb;
 
always
begin 
clk =1;
#10;
clk =0;
#10;
end
 
    // Inputs
    reg clk;
    reg start;
    reg [31:0] xn_re;
    reg [31:0] xn_im;
    reg fwd_inv;
    reg fwd_inv_we;
 
 
    // Outputs
    wire rfd;
    wire [2:0] xn_index;
    wire busy;
    wire edone;
    wire done;
    wire dv;
    wire [2:0] xk_index;
    wire [31:0] xk_re;
    wire [31:0] xk_im;
 
    // Instantiate the Unit Under Test (UUT)
    fft1 uut (
        .clk(clk), 
        .start(start), 
        .xn_re(xn_re), 
        .xn_im(xn_im), 
        .fwd_inv(fwd_inv), 
        .fwd_inv_we(fwd_inv_we),
        .rfd(rfd), 
        .xn_index(xn_index), 
        .busy(busy), 
        .edone(edone), 
        .done(done), 
        .dv(dv), 
        .xk_index(xk_index), 
        .xk_re(xk_re), 
        .xk_im(xk_im)
    );
 
    initial begin
        // Initialize Inputs
        clk = 0;
        start = 0;
        xn_re = 0;
        xn_im = 0;
        fwd_inv = 0;
        fwd_inv_we = 0;
        
        // Wait 100 ns for global reset to finish
        #100;
        
        start = 1;
        fwd_inv = 1;
        fwd_inv_we = 0;        
        // Add stimulus here
        
       //#20;
        xn_re = 32'b01000000000000000000000000000000; // 2
      xn_im = 0;        
        
        #20;
        
        xn_re = 32'b01000000100000000000000000000000; //------ 4
        xn_im = 0;
        
        //#20;
        
        //xn_re = 32'b01000000111000000000000000000000; //------ 7
        //xn_im = 0;
        
        //#20;
        
        //xn_re = 32'b01000001000100000000000000000000; //------9
        //xn_im = 0;
 
       //#20;
        //xn_re = 32'b01000000010000000000000000000000; //------ 3
        //xn_im = 0; 
        
        //#20;
 
        //xn_re = 32'b01000001001000000000000000000000; //------ 10
        //xn_im = 0;
 
      //#20;
 
      //xn_re = 32'b01000001010000000000000000000000; //------ 12
        //xn_im = 0;
 
     // #20;
 
      //xn_re = 32'b01000001011100000000000000000000; //------ 15
        //xn_im = 0;
 
 
        
    end
      
endmodule


Main module


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
module fft1(clk,start,xn_re,xn_im,fwd_inv,fwd_inv_we,rfd,xn_index,busy,edone,done,dv,xk_index,xk_re,xk_im);
  
input [31:0] xn_re,xn_im;
input clk,start,fwd_inv,fwd_inv_we; 
 
 
output [31:0] xk_re,xk_im;
output [2:0] xn_index,xk_index;
output rfd,busy,done,edone,dv; 
  
reg ce=1,sclr=0; 
wire [31:0] xk_re,xk_im;
 
 
fft1_ip a1(
 
  .clk(clk), 
  .start(start),
  .ce(ce),
  .sclr(sclr),  
  .xn_re(xn_re), 
  .xn_im(xn_im), 
  .fwd_inv(fwd_inv), 
  .fwd_inv_we(fwd_inv_we),
  .rfd(rfd), 
  .xn_index(xn_index),
  .busy(busy), 
  .edone(edone), 
  .done(done), 
  .dv(dv), 
  .xk_index(xk_index), 
  .xk_re(xk_re), 
  .xk_im(xk_im) 
  
 );
 
endmodule




untitled.png
 
Last edited by a moderator:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top